Product details


Technology Family ALS Function Decoder, Demultiplexer Configuration 3:8, 1:8, 2:4, 1:4 Channels (#) 1, 2 VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Input type TTL Output type TTL open-in-new Find other Encoders & decoders

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 open-in-new Find other Encoders & decoders


  • Applications:
    • Dual 2-Line to 4-Line Decoder
    • Dual 1-Line to 4-Line Demultiplexer
    • 3-Line to 8-Line Decoder
    • 1-Line to 8-Line Demultiplexer
  • Individual Strobes Simplify Cascading for Decoding or Demultiplexing Larger Words
  • Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic (N) 300-mil DIPs
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One of the main applications of the SN74ALS156 is as a dual 1-line to 4-line decoder/demultiplexer with individual strobes (G\) and common binary-address inputs in a single 16-pin package. When both sections are enabled, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit enabling or disabling each of the 4-bit sections, as desired.

Data applied to input 1C is inverted at its outputs and data applied at input 2C\ is not inverted through its outputs. The inverter following the 1C data input permits use of the SN74ALS156 as a 3-line to 8-line demultiplexer without external gating. All inputs are clamped with high-performance Schottky diodes to suppress line ringing and simplify system design.

The SN74ALS156 is characterized for operation from 0°C to 70°C.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 12
Type Title Date
* Datasheet Decoder/Demultiplexer With Open-Collector Outputs datasheet (Rev. C) May 01, 1996
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Advanced Schottky (ALS and AS) Logic Families Aug. 01, 1995

Design & development

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Hardware development

document-generic User guide
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options
SOIC (D) 16 View options

Ordering & quality

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