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SN74AUP1G04

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Low-Power Single Inverter Gate

Data sheet
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Low-Power Single Inverter Gate

SN74AUP1G04

ACTIVE
Data sheet Order now

Product details

Parameters

Technology Family AUP VCC (Min) (V) 0.8 VCC (Max) (V) 3.6 Channels (#) 1 IOL (Max) (mA) 4 IOH (Max) (mA) -4 ICC (Max) (uA) 10 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Data rate (Mbps) 200 Rating Catalog open-in-new Find other Inverting buffer/driver

Package | Pins | Size

DSBGA (YFP) 4 0 mm² .8 x .8 SOT-23 (DBV) 5 5 mm² 2.9 x 1.6 SOT-5X3 (DRL) 5 2 mm² 1.65 x 1.2 SOT-SC70 (DCK) 5 4 mm² 2 x 2.1 USON (DRY) 6 1 mm² 1.5 x 1 X2SON (DPW) 5 1 mm² .8 x .8 X2SON (DSF) 6 1 mm² 1 x 1 open-in-new Find other Inverting buffer/driver

Features

  • Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
  • Low Static-Power Consumption
    (ICC = 0.9 μA Max)
  • Low Dynamic-Power Consumption
    (Cpd = 4.1 pF Typ at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typ)
  • Low Noise − Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typ at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 3.9 ns Max at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
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Description

The SN74AUP1G04 device is a single inverter gate performs the Boolean function Y = A.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 8
Type Title Date
* Datasheet SN74AUP1G04 Low-Power Single Inverter Gate datasheet (Rev. K) Jun. 26, 2014
Selection guide Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Application note Designing and Manufacturing with TI's X2SON Packages Aug. 23, 2017
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
White paper Solving CMOS Transition Rate Issues Using Schmitt Trigger Solution (Rev. A) May 01, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Understanding Schmitt Triggers Sep. 21, 2011
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
View details

Design tools & simulation

SIMULATION MODEL Download
SCEM423.ZIP (65 KB) - IBIS Model
SIMULATION MODEL Download
SCEM692.ZIP (7 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
HDMI 2.0 ESD Protection Reference Design
TIDA-050001 — This reference design is to show two distinct ways to protect the TMDS lines of a HDMI 2.0 drivers and retimers from electrostatic discharge (ESD). The HDMI standard is used in many applications from set-topboxes to notebooks to TV's. Since these ports are almost always external they are susceptible (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
DSBGA (YFP) 4 View options
SC70 (DCK) 5 View options
SON (DRY) 6 View options
SON (DSF) 6 View options
SOT-23 (DBV) 5 View options
SOT-5X3 (DRL) 5 View options
X2SON (DPW) 5 View options

Ordering & quality

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  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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