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Inverting buffers & drivers

SN74AUP1G04

ACTIVE

Single 0.8-V to 3.6-V low power inverter

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Data sheet

SN74AUP1G04

ACTIVE
Data sheet Order now

Product details

Technology family AUP Number of channels 1 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 10 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP Number of channels 1 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 10 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YFP) 4 1 mm² (— mm × — mm) USON (DRY) 6 1.45 mm² (1.45 mm × 1 mm) SOT-5X3 (DRL) 5 2.56 mm² (1.6 mm × 1.6 mm) X2SON (DSF) 6 1 mm² (1 mm × 1 mm) X2SON (DPW) 5 0.64 mm² (0.8 mm × 0.8 mm) SOT-SC70 (DCK) 5 4.2 mm² (2 mm × 2.1 mm) SOT-23 (DBV) 5 8.12 mm² (2.9 mm × 2.8 mm)
  • Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
  • Low Static-Power Consumption
    (ICC = 0.9 μA Max)
  • Low Dynamic-Power Consumption
    (Cpd = 4.1 pF Typ at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typ)
  • Low Noise − Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typ at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 3.9 ns Max at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
  • Low Static-Power Consumption
    (ICC = 0.9 μA Max)
  • Low Dynamic-Power Consumption
    (Cpd = 4.1 pF Typ at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typ)
  • Low Noise − Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typ at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 3.9 ns Max at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

The SN74AUP1G04 device is a single inverter gate performs the Boolean function Y = A.

The SN74AUP1G04 device is a single inverter gate performs the Boolean function Y = A.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74AUP1G04 Low-Power Single Inverter Gate datasheet (Rev. K) PDF | HTML Jun 26, 2014
Application brief Understanding Schmitt Triggers (Rev. B) PDF | HTML Apr 17, 2025
Application note Designing and Manufacturing with TI's X2SON Packages Aug 23, 2017
White paper Solving CMOS Transition Rate Issues Using Schmitt Trigger Solution (Rev. A) May 1, 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
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Evaluation board

5-8-NL-LOGIC-EVM — Generic logic and translation EVM supporting 5 to 8 pin DPW, DQE, DRY, DSF, DTM, DTQ and DTT pkgs

Generic EVM designed to support any logic or translation device that has a DTT, DRY, DPW, DTM, DQE, DQM, DSF, or DTQ package. Board design allows for flexible evaluation.

User guide: PDF | HTML
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Simulation model

SN74AUP1G04 Behavioral SPICE Model

SCEM692.ZIP (7 KB) - PSpice model
Supported products & hardware
Simulation model

SN74AUP1G04 IBIS Model

SCEM423.ZIP (65 KB) - IBIS model
Supported products & hardware
Reference design

TIDA-050001 — HDMI 2.0 ESD Protection Reference Design

This reference design is to show two distinct ways to protect the TMDS lines of a HDMI 2.0 drivers and retimers from electrostatic discharge (ESD). The HDMI standard is used in many applications from set-topboxes to notebooks to TV's. Since these ports are almost always external they are (...)

Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
DSBGA (YFP) 4 Ultra Librarian
USON (DRY) 6 Ultra Librarian
SOT-5X3 (DRL) 5 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian
X2SON (DPW) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
SOT-23 (DBV) 5 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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