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SN74AUP1G74

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Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

Data sheet
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Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

SN74AUP1G74

ACTIVE
Data sheet Order now

Product details

Parameters

Channels (#) 1 Technology Family AUP VCC (Min) (V) 0.8 VCC (Max) (V) 3.6 Input type Standard CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 160 IOL (Max) (mA) 4 IOH (Max) (mA) -4 Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Partial power down (Ioff) open-in-new Find other D-type flip-flop

Package | Pins | Size

DSBGA (YFP) 8 0 mm² .8 x 1.6 DSBGA (YZP) 8 3 mm² .928 x 1.928 UQFN (RSE) 8 2 mm² 2 x 1.5 VSSOP (DCU) 8 6 mm² 2 x 3.1 X2SON (DQE) 8 1 mm² 1.4 x 1 open-in-new Find other D-type flip-flop

Features

  • Available in the Texas Instruments NanoStar Package
  • Low Static-Power Consumption: ICC = 0.9 μA Maximum
  • Low Dynamic-Power Consumption: Cpd = 5.5 pF Typical at 3.3 V
  • Low Input Capacitance: Ci = 1.5 pF Typical
  • Low Noise – Overshoot and Undershoot < 10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 5 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

    • NanoStar Is a trademark of Texas Instruments. All other trademarks are the property of their respective owners

  • APPLICATIONS
    • Servers
    • LED Displays
    • Network Switches
    • Telecom Infrastructure
    • Motor Drivers
    • I/O Expanders
    •  open-in-new Find other D-type flip-flop

    Description

    The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in ).

     open-in-new Find other D-type flip-flop
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    Technical documentation

    = Top documentation for this product selected by TI
    No results found. Please clear your search and try again. View all 8
    Type Title Date
    * Datasheet SN74AUP1G74 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset datasheet (Rev. D) Dec. 29, 2015
    Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
    Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
    Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
    Technical articles A race against the clock: how to determine the power-up states of clocked devices Mar. 06, 2015
    Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
    Application notes Understanding Schmitt Triggers Sep. 21, 2011
    Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004

    Design & development

    For additional terms or required resources, click any title below to view the detail page where available.

    Hardware development

    EVALUATION BOARDS Download
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    Description
    Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
    Features
    • Board design allows for versatility in evaluation
    • Supports a wide-range of logic devices
    View details
    EVALUATION BOARDS Download
    document-generic User guide
    999
    Description

    This board supports: TAS2555YZEVM, TAS2557EVM and TAS2559EVM.

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    Features
    • Easily and quickly characterize speakers
    • Quick connection to TI Smart Amplifier EVMs
    • Microphone included for SPL measurements
    • Laser input for speaker excursion measurements
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    CAD/CAE symbols

    Package Pins Download
    DSBGA (YFP) 8 View options
    DSBGA (YZP) 8 View options
    UQFN (RSE) 8 View options
    VSSOP (DCU) 8 View options
    X2SON (DQE) 8 View options

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