SN74HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset | TI.com

SN74HCT74
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Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset - SN74HCT74
Datasheet
 

Description

The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

Features

  • Operating Voltage Range of 4.5 V to 5.5 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 40-µA Max ICC
  • Typical tpd = 17 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Inputs Are TTL-Voltage Compatible

Parametrics

Compare all products in D-type flip-flop Email Download to Excel
Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) IOL (Max) (mA) IOH (Max) (mA) Rating Package Group
SN74HCT74 Order now HCT     TTL     CMOS     4.5     5.5     4     -4     Catalog     PDIP | 14
SOIC | 14
SO | 14
SSOP | 14
TSSOP | 14    
SN54HCT74 Samples not available HCT     TTL     CMOS     4.5     5.5     4     -4     Military     CDIP | 14
CFP | 14
LCCC | 20