Product details

Number of channels (#) 2 Technology Family LS Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock Frequency (MHz) 13 ICC (Max) (uA) 6000 IOL (Max) (mA) 8 IOH (Max) (mA) -0.4 Features Negative edge triggered, High speed (tpd 10-50ns), Clear
Number of channels (#) 2 Technology Family LS Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock Frequency (MHz) 13 ICC (Max) (uA) 6000 IOL (Max) (mA) 8 IOH (Max) (mA) -0.4 Features Negative edge triggered, High speed (tpd 10-50ns), Clear
PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6
  • Package Options Include Plastic “Small Outline" Packages, Flat Packages, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

 

  • Package Options Include Plastic “Small Outline" Packages, Flat Packages, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

 

The '73, and 'H73, contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '73, and 'H73, are positive pulse-triggered flip-flops. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS73A contains two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.

The SN5473, SN54H73, and the SN54LS73A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7473, and the SN74LS73A are characterized for operation from 0°C to 70°C.

 

The '73, and 'H73, contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '73, and 'H73, are positive pulse-triggered flip-flops. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS73A contains two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.

The SN5473, SN54H73, and the SN54LS73A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7473, and the SN74LS73A are characterized for operation from 0°C to 70°C.

 

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Technical documentation

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Type Title Date
* Data sheet Dual J-K Flip-Flops With Clear datasheet 01 Mar 1988
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) 06 Feb 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Designing with the SN54/74LS123 (Rev. A) 01 Mar 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

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PDIP (N) 14 View options
SOIC (D) 14 View options

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