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SN74LV8T164

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1.65-V to 5.5-V 8-bit, parallel-out serial shift registers with logic level shifter

Product details

Operating temperature range (°C) -40 to 125 Rating Automotive, Catalog
Operating temperature range (°C) -40 to 125 Rating Automotive, Catalog
TSSOP (PW) 14 32 mm² 5 x 6.4 WQFN (BQA) 14 7.5 mm² 3 x 2.5
  • Latching logic with known power-up state provides consistent start-up behavior
  • Wide operating range of 1.65V to 5.5V
  • 5.5V tolerant input pins
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
    • Up translation:
      • 1.2V to 1.8V
      • 1.5V to 2.5V
      • 1.8V to 3.3V
      • 3.3V to 5.0V
    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • Up to 150Mbps with 5V or 3.3V VCC
  • Supports standard function pinout
  • Latch-up performance exceeds 250mAper JESD 17
  • Latching logic with known power-up state provides consistent start-up behavior
  • Wide operating range of 1.65V to 5.5V
  • 5.5V tolerant input pins
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
    • Up translation:
      • 1.2V to 1.8V
      • 1.5V to 2.5V
      • 1.8V to 3.3V
      • 3.3V to 5.0V
    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • Up to 150Mbps with 5V or 3.3V VCC
  • Supports standard function pinout
  • Latch-up performance exceeds 250mAper JESD 17

The SN74LV8T164 device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The SN74LV8T164 device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

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Technical documentation

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* Data sheet SN74LV8T164 8-Bit Parallel-Load Shift Register With Logic-Level Shifter datasheet PDF | HTML 22 Mar 2024

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
Not available on TI.com
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian

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