Single retriggerable monostable multivibrator with Schmitt-trigger inputs

SN74LVC1G123

ACTIVE

Product details

Number of channels (#) 1 Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Technology Family LVC Input type Schmitt-Trigger Output type Push-Pull ICC (uA) 20 IOL (Max) (mA) 32 IOH (Max) (mA) -32 Features Over-voltage tolerant inputs, Partial power down (Ioff), High speed (tpd 10-50ns), Balanced outputs
Number of channels (#) 1 Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Technology Family LVC Input type Schmitt-Trigger Output type Push-Pull ICC (uA) 20 IOL (Max) (mA) 32 IOH (Max) (mA) -32 Features Over-voltage tolerant inputs, Partial power down (Ioff), High speed (tpd 10-50ns), Balanced outputs
DSBGA (YZP) 8 3 mm² .928 x 1.928 SSOP (DCT) 8 8 mm² 3 x 2.8 SSOP (DCT) 8 8 mm² 2.95 x 2.80 VSSOP (DCU) 8 6 mm² 2 x 3.1
  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 8 ns at 3.3 V
  • Supports Mixed-Mode Voltage Operation on
    All Ports
  • Supports Down Translation to VCC
  • Schmitt-Trigger Circuitry on A and B Inputs for
    Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low
     Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses, Up to
    100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 8 ns at 3.3 V
  • Supports Mixed-Mode Voltage Operation on
    All Ports
  • Supports Down Translation to VCC
  • Schmitt-Trigger Circuitry on A and B Inputs for
    Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low
     Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses, Up to
    100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65-V to 5.5-V VCC operation.

This monostable multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65-V to 5.5-V VCC operation.

This monostable multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

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Technical documentation

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Type Title Date
* Data sheet SN74LVC1G123 Single Retriggerable Monostable Multivibrator With Schmitt-Trigger Inputs datasheet (Rev. D) 22 Jun 2015
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Application note Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) 13 Mar 2020
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic EVM supporting 5 through 8 pin DCK, DCT, DCU, DRL, and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
In stock
Limit: 5
Simulation model

HSPICE Model for SN74LVC1G123

SCEJ262.ZIP (98 KB) - HSpice Model
Simulation model

SN74LVC1G123 IBIS Model

SCEM427.ZIP (45 KB) - IBIS Model
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DSBGA (YZP) 8 View options
SM8 (DCT) 8 View options
VSSOP (DCU) 8 View options

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