2-bit level-translating 1-MHz I2C/SMBus buffer/repeater
Product details
Parameters
Package | Pins | Size
Features
- Two-Channel Bidirectional I2C Buffer
- Support for Standard Mode, Fast Mode (400 kHz), and Fast Mode+ (1 Mhz) I2C Operation
- Operating Supply Voltage Range of 0.8 V to 5.5 V on A-Side
- Operating Supply Voltage Range of 2.2 V to 5.5 V on B-Side
- Voltage-Level Translation From 0.8 V to 5.5 V and 2.2 V to 5.5 V
- Footprint and Function Replacement for TCA9517
- Active-High Repeater-Enable Input
- Open-Drain I2C I/O
- 5.5-V Tolerant I2C and Enable Input Support
- Mixed-Mode Signal Operation
- Lockup-Free Operation
- Support for Clock Stretching and Multiple Master Arbitration Across The Device
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 4000-V Human-Body Model (A114-A)
- 1500-V Charged-Device Model (C101)
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Description
The TCA9617A is a BiCMOS dual bidirectional buffer intended for I2C bus and SMBus systems. It can provide bidirectional voltage-level translation (up-translation and down-translation) between low voltages (down to 0.8 V) and higher voltages (2.2 V to 5.5 V) in mixed-mode applications. This device enables I2C and similar bus systems to be extended, without degradation of performance even during level shifting.
The TCA9617A buffers both the serial data (SDA) and the serial clock (SCL) signals on the I2C bus, allowing two buses of 550-pF or greater bus capacitance to be connected in an I2C application. This device can also be used to isolate two halves of a bus for voltage and capacitance.
Same functionality and pinout but is not an equivalent to the compared device:
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | TCA9617A Level-Translating FM+ I2C Bus Repeater datasheet (Rev. B) | Dec. 05, 2018 |
Application note | Why, When, and How to use I2C Buffers | May 23, 2018 | |
Application note | Choosing the Correct I2C Device for New Designs | Sep. 07, 2016 | |
Selection guide | I2C Infographic Flyer | Dec. 03, 2015 | |
Application note | Understanding the I2C Bus | Jun. 30, 2015 | |
Application note | Maximum Clock Frequency of I2C Bus Using Repeaters | May 15, 2015 | |
Application note | I2C Bus Pull-Up Resistor Calculation | Feb. 13, 2015 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Features
- GUI-based web application
- Exportable designs
- JSON file uploader
- Bill of materials generator
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
VSSOP (DGK) | 8 | View options |
Ordering & quality
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- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
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Support & training
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