The UCC23511-Q1 is an Opto-compatible, single-channel, isolated gate driver for IGBTs, MOSFETs and SiC MOSFETs, with 1.5-A source and 2-A sink peak output current and 5.7-kVRMS reinforced isolation rating. The high supply voltage range of 33-V allows the use of bipolar supplies to effectively drive IGBTs and SiC power FETs. UCC23511-Q1 can drive both low side and high side power FETs. Key features and characteristics bring significant performance and reliability upgrades over standard opto-coupler based gate drivers while maintaining pin-to-pin compatibility in both schematic and layout design. Performance highlights include high common mode transient immunity (CMTI), low propagation delay, and small pulse width distortion. Tight process control results in small part-to-part skew. The input stage is an emulated diode (ediode) which means long term reliability and excellent aging characteristics compared to traditional LEDs found in optocoupler gate drivers. It is offered in a stretched SO6 package with >8.5mm creepage and clearance, and a mold compound from material group I which has a comparative tracking index (CTI) >600V. UCC23511-Q1’s high performance and reliability makes it ideal for use in automotive motor drives such as the traction inverter, on-board chargers, DC charging stations, and automotive HVAC and heating systems. The higher operating temperature opens up opportunities for applications not previously able to be supported by traditional optocouplers.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | UCC23511-Q1 1.5-A Source, 2-A Sink, 5.7-kVRMS Opto-Compatible Single-Channel Iso datasheet (Rev. A) | 09 Mar 2021 | |
| Application note | The Use and Benefits of Ferrite Beads in Gate Drive Circuits | PDF | HTML | 16 Dec 2021 | |
| Functional safety information | UCC23x1x-Q1, Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA | PDF | HTML | 18 Feb 2021 | |
| EVM User's guide | UCC2351x Evaluation Module User’s Guide (Rev. B) | 09 Sep 2019 | ||
| Technical article | How to achieve higher system robustness in DC drives, part 3: minimum input pulse | 19 Sep 2018 | ||
| Technical article | How to achieve higher system robustness in DC drives, part 2: interlock and deadtime | 30 May 2018 | ||
| Technical article | Boosting efficiency for your solar inverter designs | 24 May 2018 | ||
| Technical article | How to achieve higher system robustness in DC drives, part 1: negative voltage | 17 Apr 2018 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | Download |
|---|---|---|
| SOIC (DWY) | 6 | View options |
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