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AM5K2E02

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Datenblatt

AM5K2E02

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

CPU 2 Arm Cortex-A15 Frequency (MHz) 1250, 1400 Protocols Ethernet PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
CPU 2 Arm Cortex-A15 Frequency (MHz) 1250, 1400 Protocols Ethernet PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt AM5K2E04/02 Multicore ARM KeyStone II System-on-Chip (SoC) datasheet (Rev. D) 11.03.2015
* Errata AM5K2E04/02 KeyStone SoC Silicon Errata (Silicon Rev 1.0) (Rev. B) 20.08.2015
Anwendungshinweis DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 07.07.2022
Anwendungshinweis Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 04.06.2019
Anwendungshinweis Keystone Multicore Device Family Schematic Checklist PDF | HTML 17.05.2019
Anwendungshinweis KeyStone II DDR3 interface bring-up PDF | HTML 07.03.2019
Benutzerhandbuch How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 24.09.2018
Benutzerhandbuch KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 21.08.2017
Anwendungshinweis Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 14.08.2017
Benutzerhandbuch Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 26.07.2017
Anwendungshinweis Power Consumption Summary for K2E System-on-Chip (SoC) Device Family 14.06.2017
Anwendungshinweis Clocking Spreadsheet for K2E Device Family 26.01.2017
Benutzerhandbuch Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 27.07.2016
Anwendungshinweis Power Management of KS2 Device (Rev. C) 15.07.2016
Anwendungshinweis Throughput Performance Guide for KeyStone II Devices (Rev. B) 22.12.2015
Anwendungshinweis Keystone II DDR3 Debug Guide 16.10.2015
Benutzerhandbuch Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) PDF | HTML 06.05.2015
Benutzerhandbuch Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) 28.04.2015
Benutzerhandbuch Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 09.04.2015
Benutzerhandbuch DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 27.03.2015
Whitepaper Save power and costs with TI's K2E on-chip networking features 25.03.2015
Anwendungshinweis Keystone II DDR3 Initialization 26.01.2015
Benutzerhandbuch Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 04.09.2014
Whitepaper KeyStone™-II-based processors: 10G Ethernet as an optical interface 25.08.2014
Benutzerhandbuch Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide 19.08.2014
Benutzerhandbuch Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide 19.08.2014
Whitepaper Differentiating AM5K2E02 and AM5K2E04 SoCs from Alternate ARM® Cortex®-A15 Devic 14.08.2014
Benutzerhandbuch Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide 13.08.2014
Anwendungshinweis Hardware Design Guide for KeyStone II Devices 24.03.2014
Benutzerhandbuch PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 30.09.2013
Benutzerhandbuch Debug and Trace for KeyStone II Devices User's Guide 26.07.2013
Benutzerhandbuch ARM Bootloader User Guide for KeyStone II Devices 21.07.2013
Benutzerhandbuch Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 28.06.2013
Benutzerhandbuch HyperLink for KeyStone Devices User's Guide (Rev. C) 28.05.2013
Benutzerhandbuch Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 12.11.2012
Product overview Industrial Imaging: Applications of the K2H and K2E platforms 09.11.2012
Product overview Video Infrastructure - Applications of the K2E, K2H platforms 09.11.2012
Product overview OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A) 05.11.2012
Benutzerhandbuch ARM CorePac User Guide for KeyStone II Devices 31.10.2012
Anwendungshinweis Multicore Programming Guide (Rev. B) 29.08.2012
Benutzerhandbuch Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 30.03.2012
Benutzerhandbuch Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 27.03.2012
Benutzerhandbuch 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 22.03.2012
Anwendungshinweis PCIe Use Cases for KeyStone Devices 13.12.2011
Benutzerhandbuch Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 02.09.2011
Benutzerhandbuch External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 24.05.2011
Anwendungshinweis Optimizing Loops on the C66x DSP 09.11.2010
Benutzerhandbuch General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 09.11.2010
Anwendungshinweis Clocking Design Guide for KeyStone Devices 09.11.2010
Benutzerhandbuch Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 09.11.2010
Benutzerhandbuch C66x DSP Cache User's Guide 09.11.2010
Benutzerhandbuch Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide 09.11.2010

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