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AM5K2E04

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Sitara-Prozessor: Vierfach-Arm Cortex-A15

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Datenblatt

AM5K2E04

AKTIV
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Produktdetails

CPU 4 Arm Cortex-A15 Frequency (MHz) 1250, 1400 Protocols Ethernet PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
CPU 4 Arm Cortex-A15 Frequency (MHz) 1250, 1400 Protocols Ethernet PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (ABD) 1089 729 mm² (27 mm × 27 mm)
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt AM5K2E04/02 Multicore ARM KeyStone II System-on-Chip (SoC) datasheet (Rev. D) 11.03.2015
* Errata AM5K2E04/02 KeyStone SoC Silicon Errata (Silicon Rev 1.0) (Rev. B) 20.08.2015
Benutzerhandbuch ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 30.03.2023
Benutzerhandbuch ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 30.03.2023
Anwendungshinweis DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 07.07.2022
Anwendungshinweis Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 04.06.2019
Anwendungshinweis Keystone Multicore Device Family Schematic Checklist PDF | HTML 17.05.2019
Anwendungshinweis KeyStone II DDR3 interface bring-up PDF | HTML 07.03.2019
Benutzerhandbuch How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 24.09.2018
Benutzerhandbuch KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 21.08.2017
Anwendungshinweis Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 14.08.2017
Benutzerhandbuch Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 26.07.2017
Anwendungshinweis Power Consumption Summary for K2E System-on-Chip (SoC) Device Family 14.06.2017
Anwendungshinweis Clocking Spreadsheet for K2E Device Family 26.01.2017
Benutzerhandbuch Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 27.07.2016
Anwendungshinweis Power Management of KS2 Device (Rev. C) 15.07.2016
Anwendungshinweis Throughput Performance Guide for KeyStone II Devices (Rev. B) 22.12.2015
Anwendungshinweis Keystone II DDR3 Debug Guide 16.10.2015
Benutzerhandbuch Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) PDF | HTML 06.05.2015
Benutzerhandbuch Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) 28.04.2015
Benutzerhandbuch Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 09.04.2015
Benutzerhandbuch DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 27.03.2015
Whitepaper Save power and costs with TI's K2E on-chip networking features 25.03.2015
Anwendungshinweis Keystone II DDR3 Initialization 26.01.2015
Benutzerhandbuch Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 04.09.2014
Whitepaper KeyStone™-II-based processors: 10G Ethernet as an optical interface 25.08.2014
Benutzerhandbuch Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide 19.08.2014
Benutzerhandbuch Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide 19.08.2014
Whitepaper Differentiating AM5K2E02 and AM5K2E04 SoCs from Alternate ARM® Cortex®-A15 Devic 14.08.2014
Benutzerhandbuch Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide 13.08.2014
Anwendungshinweis Hardware Design Guide for KeyStone II Devices 24.03.2014
Benutzerhandbuch PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 30.09.2013
Benutzerhandbuch Debug and Trace for KeyStone II Devices User's Guide 26.07.2013
Benutzerhandbuch ARM Bootloader User Guide for KeyStone II Devices 21.07.2013
Benutzerhandbuch Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 28.06.2013
Benutzerhandbuch HyperLink for KeyStone Devices User's Guide (Rev. C) 28.05.2013
Benutzerhandbuch 10 Gigabit Ethernet Switch Subsystem User Guide for KeyStone II Devices 08.02.2013
Benutzerhandbuch Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 12.11.2012
Product overview Industrial Imaging: Applications of the K2H and K2E platforms 09.11.2012
Product overview Video Infrastructure - Applications of the K2E, K2H platforms 09.11.2012
Benutzerhandbuch ARM CorePac User Guide for KeyStone II Devices 31.10.2012
Anwendungshinweis Multicore Programming Guide (Rev. B) 29.08.2012
Benutzerhandbuch Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 30.03.2012
Benutzerhandbuch Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 27.03.2012
Benutzerhandbuch 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 22.03.2012
Anwendungshinweis PCIe Use Cases for KeyStone Devices 13.12.2011
Benutzerhandbuch Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 02.09.2011
Benutzerhandbuch External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 24.05.2011
Anwendungshinweis Optimizing Loops on the C66x DSP 09.11.2010
Benutzerhandbuch General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 09.11.2010
Anwendungshinweis Clocking Design Guide for KeyStone Devices 09.11.2010
Benutzerhandbuch Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 09.11.2010
Benutzerhandbuch C66x DSP Cache User's Guide 09.11.2010
Benutzerhandbuch Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide 09.11.2010

Design und Entwicklung

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Entwicklungskit

EVMK2EX — K2E-Entwicklungsplatine

Das EVMK2EX ist ein voll ausgestattetes Entwicklungstool für die SoC-Bausteine 66AK2Exx und AM5K2Exx auf Basis von KeyStone II. Steigen Sie gleich heute in die Entwicklung von universell einsetzbaren Embedded-Computersystemen für Industrie-, unternehmenskritische und Netzwerkanwendungen ein. Diese (...)

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TMDSEMU200-U — XDS200-USB-Debug-Tastkopf

Der XDS200 ist ein Debug-Tastkopf (Emulator) zum Debugging von Embedded-Bausteinen von TI. Für die meisten Bausteine wird die Verwendung der neueren, kostengünstigeren XDS110 (www.ti.com/tool/TMDSEMU110-U) empfohlen. Der XDS200 unterstützt eine große Zahl von Standards (IEEE1149.1, IEEE1149.7, SWD) (...)

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TMDSEMU560V2STM-U — XDS560™-Software v2 – System-Trace-USB-Debug-Sonde

XDS560v2 ist die Debug-Sonde mit der höchsten Leistung der XDS560™-Produktfamilie und unterstützt sowohl den herkömmlichen JTAG-Standard (IEEE1149.1) als auch cJTAG (IEEE1149.7).  Beachten Sie, dass das Serial Wire Debugging (SWD) nicht unterstützt wird.

Alle XDS-Debug-Sonden unterstützen Core- und (...)

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Debug-Tastkopf

TMDSEMU560V2STM-UE — XDS560v2 System-Trace-USB-und Ethernet-Debug-Tastkopf

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Software-Entwicklungskit (SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-K2E — Linux Processor SDK for K2E

 

Das Prozessor-SDK (Software Development Kit) ist eine vereinheitliche Softwareplattform für alle Embedded-Prozessoren von TI. Es ist einfach einzurichten und bringt bereits alle Funktionen für den schnellen Zugriff auf Benchmarks und Demos mit.  Alle Versionen des Prozessor-SDK lassen sich (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-RT-K2E — Linux-RT Processor SDK for K2E

 

Das Prozessor-SDK (Software Development Kit) ist eine vereinheitliche Softwareplattform für alle Embedded-Prozessoren von TI. Es ist einfach einzurichten und bringt bereits alle Funktionen für den schnellen Zugriff auf Benchmarks und Demos mit.  Alle Versionen des Prozessor-SDK lassen sich (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-RTOS-K2E — RTOS Processor SDK for K2E

 

Das Prozessor-SDK (Software Development Kit) ist eine vereinheitliche Softwareplattform für alle Embedded-Prozessoren von TI. Es ist einfach einzurichten und bringt bereits alle Funktionen für den schnellen Zugriff auf Benchmarks und Demos mit.  Alle Versionen des Prozessor-SDK lassen sich (...)

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IDE, Konfiguration, Compiler oder Debugger

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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Simulationsmodell

AM5K2E04 AM5K2E02 ABD BSDL Model

SPRM623.ZIP (28 KB) - BSDL-Modell
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Simulationsmodell

AM5K2E04 AM5K2E02 ABD IBIS Model

SPRM621.ZIP (2180 KB) - IBIS-Modell
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AM5K2E04 AM5K2E02 ABD Thermal Model

SPRM622.ZIP (5 KB) - Wärmemodell
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AM5K2E04 and AM5K2E02 Power Consumption Model (Rev. A)

SPRM653A.ZIP (142 KB) - Stromversorgungsmodell
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KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI-Modell
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Berechnungstool

CLOCKTREETOOL — Taktbaum-Tool für Sitara, Automobilanwendungen, Sichtanalytik und digitale Signalprozessoren

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
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Referenzdesign

TIDEP0026 — Referenzdesign für K2E Taktgenerierung

A single clock source should not be used to drive multiple clock inputs for a high-performance processor device, such as multicore ARM Cortex-A15 based 66AK2Ex and AM5K2Ex processors, since excessive loading, reflections, and noise will negatively impact performance. These can be avoided through (...)

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Referenzdesign

TIDEP0031 — Stromversorgungssequenzierung für K2E mit UCD9090 und PMBus

The K2E devices require power supplies to be sequenced in a proper order. This design demonstrates power sequencing for the 66AK2Ex and AM5K2Ex families of KeyStone II ARM+DSP and ARM-only multicore processors by use of the UCD9090. The UCD9090 is a 10-rail PMBus/I2C addressable power-supply (...)

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Referenzdesign

TIDEP0041 — Generierung der AVS SmartReflex-Kernspannung, PMBus für K2E – Referenzdesign

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage without the need for any software. The circuit is currently implemented on the XEVMK2EX.

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Referenzdesign

TIDEP0042 — Generierung der AVS SmartReflex-Kernspannung für K2E mit TPS544C25 und PMBus – Referenzdesign

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage using software and the PMBus interface of the TPS544C25. The circuit can be implemented on the XEVMK2EX.

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