*FAST is a Registered Trademark of Fairchild Semiconductor Corp.
The RCA CD54/74AC240, CD54/74AC241, and CD54/74AC244 and the CD54/74ACT240, CD54/74ACT241, and CD54/74ACT244 3-state octal buffer/line drivers use the RCA ADVANCED CMOS technology. The CD54/74AC/ACT240 and CD54/74AC/ACT244 have active-LOW output enables (10E\, 2OE\). The CD54/74AC/ACT241 has one active-LOW (10E\) and one active-HIGH (20E) output enable.
The CD74AC240 and CD74ACT240 are supplied in 20-lead dual-in-line plastic packages (E suffix) and 20-lead small-outline packages (M and M96 suffixes). The CD74AC241 is supplied in 20-lead dual-in-line plastic packages (E suffix) and the CD74ACT241 is supplied in 20-lead dual-in-line plastic packages (E suffix) and 20-lead small-outline packages (M96 suffix). The CD74AC244 and CD74ACT244 are supplied in 20-lead dual-in-line plastic packages (E suffix), 20-lead small-outline packages (M and M96 suffixes), and 20-lead shrink small-outline packages (SM96 suffix). These package types are operable over the following temperature ranges: Commercial (0 to 70°C); Industrial (–40 to +85°C); and Extended Industrial/Military (–55 to +125°C).
The CD54AC240 and CD54AC244 and the CD54ACT240, CD54ACT241, and CD54ACT244 are supplied in 20-lead hermetic dual-in-line ceramic packages (F3A suffix) and are operable over the –55 to +125°C temperature range.
| Typ | Titel | Datum | ||
|---|---|---|---|---|
| * | Data sheet | CD54/74AC240/241/244, CD54/74ACT240/241/244 datasheet (Rev. B) | 19 Jan 2004 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 26 Jul 2021 | ||
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dez 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | Selecting the Right Level Translation Solution (Rev. A) | 22 Jun 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| Application note | CMOS Power Consumption and CPD Calculation (Rev. B) | 01 Jun 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
| Application note | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 01 Apr 1996 |
Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.
Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.
| Gehäuse | Pins | Herunterladen |
|---|---|---|
| PDIP (N) | 20 | Optionen anzeigen |
| SOIC (DW) | 20 | Optionen anzeigen |
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