CDCLVP1204

Name: CDCLVP1204
Brand: TI
SKU: CDCLVP1204
Price: 1.527 USD

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Jitterarmer, wählbarer 1:1:4-Universal-zu-LVPECL-Puffer mit zwei Eingängen

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Datenblatt

document-pdfAcrobat CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer datasheet (Rev. F) (Englisch) PDF | HTML

CDCLVP1204

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Datenblatt

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Produktdetails

Number of outputs

4

Additive RMS jitter (typ) (fs)

57

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

15

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVPECL

Input type

LVCMOS, LVDS, LVPECL

Number of outputs

4

Additive RMS jitter (typ) (fs)

57

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

15

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVPECL

Input type

LVCMOS, LVDS, LVPECL

VQFN (RGT)

16

9 mm² 3 x 3

2:4 Differential Buffer
Selectable Clock Inputs Through Control Terminal
Universal Inputs Accept LVPECL, LVDS, and
LVCMOS/LVTTL
Four LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 45 mA
Very Low Additive Jitter: <100 fs, RMS in 10-kHz
to 20-MHz Offset Range:
- 57 fs, RMS (typical) at 122.88 MHz
- 48 fs, RMS (typical) at 156.25 MHz
- 30 fs, RMS (typical) at 312.5 MHz
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 450 ps
Maximum Output Skew: 15 ps
LVPECL Reference Voltage, V_{AC_REF}, Available
for Capacitive-Coupled Inputs
Industrial Temperature Range: –40°C to +85°C
Supports 105°C PCB Temperature (Measured at
Thermal Pad)
ESD Protection Exceeds 2 kV (HBM)

2:4 Differential Buffer
Selectable Clock Inputs Through Control Terminal
Universal Inputs Accept LVPECL, LVDS, and
LVCMOS/LVTTL
Four LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 45 mA
Very Low Additive Jitter: <100 fs, RMS in 10-kHz
to 20-MHz Offset Range:
- 57 fs, RMS (typical) at 122.88 MHz
- 48 fs, RMS (typical) at 156.25 MHz
- 30 fs, RMS (typical) at 312.5 MHz
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 450 ps
Maximum Output Skew: 15 ps
LVPECL Reference Voltage, V_{AC_REF}, Available
for Capacitive-Coupled Inputs
Industrial Temperature Range: –40°C to +85°C
Supports 105°C PCB Temperature (Measured at
Thermal Pad)
ESD Protection Exceeds 2 kV (HBM)

The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1204 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1204 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. The CDCLVP1204 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1204 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (V_{AC_REF}) must be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1204 is characterized for operation from –40°C to +85°C.

The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1204 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1204 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. The CDCLVP1204 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1204 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (V_{AC_REF}) must be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1204 is characterized for operation from –40°C to +85°C.

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Top-Dokumentation	Typ	Titel	Format-Optionen	Datum
*	Data sheet	CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer datasheet (Rev. F)	PDF \| HTML	03 Sep 2015
	User guide	CDCLVP1204 User's Guide		09 Jul 2009

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VQFN (RGT)	16	Ultra Librarian

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CDCLVP1204

Jitterarmer, wählbarer 1:1:4-Universal-zu-LVPECL-Puffer mit zwei Eingängen

CDCLVP1204

Produktdetails

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