CY74FCT841T

AKTIV

Latches (Typ D), 10 Bit, Bus-Schnittstelle, mit Tri-State-Ausgängen

Produktdetails

Number of channels 10 Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 200 Features Flow-through pinout, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 10 Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 200 Features Flow-through pinout, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (DW) 24 159.65 mm² 15.5 x 10.3 SSOP (DBQ) 24 51.9 mm² 8.65 x 6
  • Function, Pinout, and Drive Compatible With FCT, F, and AM29841 Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Fully Compatible With TTL Input and Output Logic Levels
  • High-Speed Parallel Latches
  • Buffered Common Latch-Enable Input
  • 3-State Outputs
  • CY54FCT841T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT841T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current

  • Function, Pinout, and Drive Compatible With FCT, F, and AM29841 Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Fully Compatible With TTL Input and Output Logic Levels
  • High-Speed Parallel Latches
  • Buffered Common Latch-Enable Input
  • 3-State Outputs
  • CY54FCT841T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT841T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current

The \x92FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The \x92FCT841T devices are buffered 10-bit-wide versions of the FCT373 function.

The \x92FCT841T devices\x92 high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The \x92FCT841T devices are buffered 10-bit-wide versions of the FCT373 function.

The \x92FCT841T devices\x92 high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet 10-Bit Latches With 3-State Outputs datasheet (Rev. A) 01 Okt 2001
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide CYFCT Parameter Measurement Information 02 Apr 2001
Selection guide Advanced Bus Interface Logic Selection Guide 09 Jan 2001

Design und Entwicklung

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Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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SOIC (DW) 24 Ultra Librarian
SSOP (DBQ) 24 Ultra Librarian

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