Gehäuseinformationen
| Gehäuse | Pins VQFN (RGZ) | 48 |
| Betriebstemperaturbereich (°C) 0 to 70 |
| Gehäusemenge | Träger 2.500 | LARGE T&R |
Merkmale von DP83867CR
- Ultra low RGMII latency TX < 90ns, RX < 290ns
- Time Sensitive Network (TSN) compliant
- Low power consumption 457 mW
- Exceeds 8000 V IEC 61000-4-2 ESD protection
- Meets EN55011 class B emission standards
- 16 programmable RGMII delay modes on RX/TX
- Integrated MDI termination resistors
- Programmable MII/GMII/RGMII termination impedance
- WoL (Wake-on-LAN) packet detection
- 25-MHz or 125-MHz synchronized clock output
- Start of Frame Detect for IEEE 1588 time stamp
- RJ45 mirror mode
- Fully compatible to IEEE 802.3 10BASE-Te, 100BASE-TX, and 1000BASE-T Specification
- Cable diagnostics
- MII, GMII and RGMII MAC interface options
- Configurable I/O voltage (3.3 V, 2.5 V, 1.8 V)
- Fast link drop mode
- JTAG support
Beschreibung von DP83867CR
The DP83867 device is a robust, low power, fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX and 1000BASE-T Ethernet protocols. Optimized for ESD protection, the DP83867 exceeds 8-kV IEC 61000-4-2 (direct contact).
The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet LANs. It interfaces directly to twisted pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit Media Independent Interface (GMII) or Reduced GMII (RGMII). The QFP package supports MII/GMII/RGMII whereas the QFN package supports RGMII.
The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It has low latency and provides IEEE 1588 Start of Frame Detection.
The DP83867 consumes only 490mW (PAP) and 457 mW (RGZ) under full operating power. Wake on LAN can be used to lower system power consumption.