DS90CR286AT-Q1

AKTIV

LVDS-Empfänger, 3,3 V, Rising Edge Data Strobe, Channel Link, 28 Bit, 66 MHz

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Datenblatt

document-pdfAcrobat DS90CR286AT-Q1 3.3 V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link 66 MHz datasheet (Rev. A) (Englisch) PDF | HTML

DS90CR286AT-Q1

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Applications

In-vehicle Infotainment (IVI)

Input compatibility

LVDS

Function

Deserializer

Output compatibility

LVCMOS

Color depth (bpp)

24

Features

Low-EMI Point-to-Point Communication

EMI reduction

LVDS

Rating

Automotive

Operating temperature range (°C)

-40 to 105

Applications

In-vehicle Infotainment (IVI)

Input compatibility

LVDS

Function

Deserializer

Output compatibility

LVCMOS

Color depth (bpp)

24

Features

Low-EMI Point-to-Point Communication

EMI reduction

LVDS

Rating

Automotive

Operating temperature range (°C)

-40 to 105

TSSOP (DGG)

56

113.4 mm² (14 mm × 8.1 mm)

20 to 66 MHz Shift Clock Support
50% Duty Cycle on Receiver Output Clock
Best–in–Class Setup & Hold Times on
Rx Outputs
Rx Power Consumption < 270 mW (typ)
at 66 MHz Worst Case
Rx Power-down Mode < 200 μW (max)
ESD Rating: 4 kV (HBM), 1 kV (CDM)
PLL Requires No External Components
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 56-Pin DGG (TSSOP) Package
Operating Temperature: −40°C to +105°C
Automotive AEC-Q100 Grade 2 Qualified

20 to 66 MHz Shift Clock Support
50% Duty Cycle on Receiver Output Clock
Best–in–Class Setup & Hold Times on
Rx Outputs
Rx Power Consumption < 270 mW (typ)
at 66 MHz Worst Case
Rx Power-down Mode < 200 μW (max)
ESD Rating: 4 kV (HBM), 1 kV (CDM)
PLL Requires No External Components
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 56-Pin DGG (TSSOP) Package
Operating Temperature: −40°C to +105°C
Automotive AEC-Q100 Grade 2 Qualified

The DS90CR286AT-Q1 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. The receiver data outputs strobe on the output clock's rising edge.

The receiver LVDS clock operates at rates from 20 to 66 MHz. The DS90CR286AT-Q1 phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into 28-bit parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps.

The DS90CR286AT-Q1 device is enhanced over prior generation receivers due to a wider data valid time on the receiver output. The DS90CR286AT-Q1 is designed for PCB board chip-to-chip OpenLDI-to-RGB bridge conversion. LVDS data transmission over cable interconnect is not recommended for this device.

Users designing a sub-system with a compatible OpenLDI transmitter and DS90CR286AT-Q1 receiver must ensure an acceptable skew margin budget (RSKM). Details regarding RSKM can be found in the Application Information section.

The DS90CR286AT-Q1 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. The receiver data outputs strobe on the output clock's rising edge.

The receiver LVDS clock operates at rates from 20 to 66 MHz. The DS90CR286AT-Q1 phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into 28-bit parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps.

The DS90CR286AT-Q1 device is enhanced over prior generation receivers due to a wider data valid time on the receiver output. The DS90CR286AT-Q1 is designed for PCB board chip-to-chip OpenLDI-to-RGB bridge conversion. LVDS data transmission over cable interconnect is not recommended for this device.

Users designing a sub-system with a compatible OpenLDI transmitter and DS90CR286AT-Q1 receiver must ensure an acceptable skew margin budget (RSKM). Details regarding RSKM can be found in the Application Information section.

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Technische Dokumentation

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Top-Dokumentation	Typ	Titel	Format-Optionen	Datum
*	Datenblatt	DS90CR286AT-Q1 3.3 V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link 66 MHz datasheet (Rev. A)	PDF \| HTML	06.12.2015
	Anwendungshinweis	High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs		09.11.2018
	Anwendungshinweis	Receiver Skew Margin for Channel Link I and FPD Link I Devices	PDF \| HTML	13.01.2016

Design und Entwicklung

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Evaluierungsplatine

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Evaluierungsplatine

FLINK3V8BT-85 — Evaluierungskit für FPD-Link-Familie von Serializer- und Deserializer-LVDS-Bausteinen

The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.

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