Gehäuseinformationen
| Gehäuse | Pins TSSOP (PW) | 16 |
| Betriebstemperaturbereich (°C) -40 to 125 |
| Gehäusemenge | Träger 92 | TUBE |
Merkmale von DS90LV049Q-Q1
- AECQ-100 Grade 1
- Up to 400 Mbps Switching Rates
- Flow-Through Pinout Simplifies PCB Layout
- 50 ps Typical Driver Channel-to-Channel Skew
- 50 ps Typical Receiver Channel-to-Channel Skew
- 3.3 V Single Power Supply Design
- TRI-STATE Output Control
- Internal Fail-Safe Biasing of Receiver Inputs
- Low Power Dissipation (70 mW at 3.3 V Static)
- High Impedance on LVDS Outputs on Power Down
- Conforms to TIA/EIA-644-A LVDS Standard
- Available in Low Profile 16 Pin TSSOP Package
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Beschreibung von DS90LV049Q-Q1
The DS90LV049Q is a dual CMOS flow-through differential line driver-receiver pair designed for applications requiring ultra low power dissipation, exceptional noise immunity, and high data throughput. The device is designed to support data rates in excess of 400 Mbps utilizing Low Voltage Differential Signaling (LVDS) technology.
The DS90LV049Q drivers accept LVTTL/LVCMOS signals and translate them to LVDS signals. The receivers accept LVDS signals and translate them to 3 V CMOS signals. The LVDS input buffers have internal failsafe biasing that places the outputs to a known H (high) state for floating receiver inputs. In addition, the DS90LV049Q supports a TRI-STATE function for a low idle power state when the device is not in use.
The EN and EN inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four gates.