Gehäuseinformationen
| Gehäuse | Pins VQFN (RQZ) | 54 |
| Betriebstemperaturbereich (°C) -40 to 150 |
| Gehäusemenge | Träger 250 | SMALL T&R |
Merkmale von LMG3425R050
- Qualified for JEDEC JEP180 for hard-switching topologies
- 600V GaN-on-Si FET with integrated gate driver
- Integrated high precision gate bias voltage
- 200V/ns FET hold-off
- 3.6MHz switching frequency
- 20V/ns to 150V/ns slew rate for optimization of switching performance and EMI mitigation
- Operates from 7.5V to 18V supply
- Robust protection
- Cycle-by-cycle overcurrent and latched short-circuit protection with < 100ns response
- Withstands 720V surge while hard-switching
- Self-protection from internal overtemperature and UVLO monitoring
- Advanced power management
- Digital temperature PWM output
- Ideal diode mode reduces third-quadrant losses
Beschreibung von LMG3425R050
The LMG3425R050 GaN FET with integrated driver and protection is targeted at switch-mode power converters and enables designers to achieve new levels of power density and efficiency.
The LMG3425R050 integrates a silicon driver that enables switching speed up to 150V/ns. TI’s integrated precision gate bias results in higher switching SOA compared to discrete silicon gate drivers. This integration, combined with TI’s low-inductance package, delivers clean switching and minimal ringing in hard-switching power supply topologies. Adjustable gate drive strength allows control of the slew rate from 20V/ns to 150V/ns, which can be used to actively control EMI and optimize switching performance.
Advanced power management features include digital temperature reporting, fault detection, and ideal diode mode. The temperature of the GaN FET is reported through a variable duty cycle PWM output, which simplifies managing device loading. Faults reported include overcurrent, short-circuit, overtemperature, VDD UVLO, and high-impedance RDRV pin. Ideal diode mode reduces third-quadrant losses by enabling dead-time control.