Gehäuseinformationen
| Gehäuse | Pins TSSOP (PW) | 20 |
| Betriebstemperaturbereich (°C) -40 to 85 |
| Gehäusemenge | Träger 2.000 | LARGE T&R |
Merkmale von SN65LVDT41
- Integrated 110-Ω nominal receiver line termination resistor
- Single 3.3-V power supply (3-V to 3.6-V range)
- Supports signaling rates of at least 250 Mbps
- Flow-through pinout simplifies PCB layout
- LVTTL-compatible logic I/Os
- ESD protection on bus pins exceeds 16 kV
- Meets or exceeds the requirements of ANSI/TIA/EIA-644A standard for LVDS
- 20-pin PW thin shrink small-outline package with 26-mil terminal pitch
Beschreibung von SN65LVDT41
The SN65LVDTxx devices are multi-channel LVDS transceivers that operate using LVDS line drivers and receivers. The SN65LVDTxx devices support signaling rates of at least 250 Mbps, and the devices operate from a single supply (typically at 3.3 V) in a 20-pin TSSOP package designed for easy PCB layout.
The SN65LVDT14 and SN65LVDT41 provide general-purpose, asymmetric, bidirectional communication with the added benefit of high noise immunity, low electromagnetic interference (EMI), and increased cable length through the use of LVDS lines. The SN65LVDT14 and SN65LVDT41 are primarily used for SPI over LVDS applications.
The SN65LVDT14 combines one LVDS line driver with four terminated LVDS line receivers in one package. The SN65LVDT14 can be used to extend asymmetric, bidirectional interfaces such as SPI over long distances, and should be located at the SPI slave.
The SN65LVDT41 combines four LVDS line drivers with a single terminated LVDS line receiver in one package. The SN65LVDT41 can be used to extend asymmetric, bidirectional interfaces such as SPI over long distances, and should be located at the SPI master.