SN74AVC2T45

AKTIV

2-Bit-Dual-Supply-Bus-Transceiver mit konfigurierbarer Spannungsumsetzung und 3-State-Ausgängen

Eine neuere Version dieses Produkts ist verfügbar

Drop-In-Ersatz mit gegenüber dem verglichenen Baustein verbesserter Funktionalität
SN74AXC2T45 AKTIV Doppel-Bit-Doppel-Supply-Bus-Transceiver mit konfigurierbarer Spannungsumsetzung Pin-to-pin upgrade with a wider voltage range and improved performance

Produktdetails

Technology family AVC Applications I2S Bits (#) 2 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 500 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 20 Features Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Automotive, Catalog Operating temperature range (°C) -40 to 125
Technology family AVC Applications I2S Bits (#) 2 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 500 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 20 Features Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Automotive, Catalog Operating temperature range (°C) -40 to 125
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 SOT-23-THN (DDF) 8 8.12 mm² 2.9 x 2.8 SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Available in the Texas Instruments NanoFree™ Package
  • VCC Isolation Feature: If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
  • Dual Supply Rail Design
  • I/Os Are 4.6V Over Voltage Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • Max Data Rates
    • 500Mbps (1.8V to 3.3V)
    • 320Mbps (<1.8V to 3.3V )
    • 320Mbps (Level-Shifting to 2.5V or 1.8V)
    • 280Mbps (Level-Shifting to 1.5V)
    • 240Mbps (Level-Shifting to 1.2V)
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
  • Available in the Texas Instruments NanoFree™ Package
  • VCC Isolation Feature: If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
  • Dual Supply Rail Design
  • I/Os Are 4.6V Over Voltage Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • Max Data Rates
    • 500Mbps (1.8V to 3.3V)
    • 320Mbps (<1.8V to 3.3V )
    • 320Mbps (Level-Shifting to 2.5V or 1.8V)
    • 280Mbps (Level-Shifting to 1.5V)
    • 240Mbps (Level-Shifting to 1.2V)
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22

This 2-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A ports are designed to track VCCA and accepts any supply voltage from 1.2V to 3.6V. The B ports are designed to track VCCB and accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage bidirectional translation and level-shifting between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR pin) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess leakage current on the internal CMOS structure.

This 2-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A ports are designed to track VCCA and accepts any supply voltage from 1.2V to 3.6V. The B ports are designed to track VCCB and accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage bidirectional translation and level-shifting between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR pin) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess leakage current on the internal CMOS structure.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet SN74AVC2T45 2-Bit, Dual Supply, Bus Transceiver with Configurable Level-Shifting and Translation datasheet (Rev. M) PDF | HTML 18 Okt 2024
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 Okt 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 Jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 Jul 2024
Application brief Future-Proofing Your Level Shifter Design with TI's Dual Footprint Packages PDF | HTML 05 Sep 2023
EVM User's guide Generic AVC and LVC Direction Controlled Translation EVM (Rev. B) 30 Jul 2021
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
EVM User's guide SN74AXC2T-SMALLPKGEVM Evaluation module user's guide 04 Jun 2019
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 30 Apr 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
More literature LCD Module Interface Application Clip 09 Mai 2003
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 20 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 Mai 2002
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 07 Jul 1999
Application note AVC Logic Family Technology and Applications (Rev. A) 26 Aug 1998

Design und Entwicklung

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Simulationsmodell

SN74AVC2T45 IBIS Model (Rev. B)

SCEM431B.ZIP (122 KB) - IBIS Model
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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
DSBGA (YZP) 8 Ultra Librarian
SOT-23-THN (DDF) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian

Bestellen & Qualität

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  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
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