Gehäuseinformationen
| Gehäuse | Pins SOIC (D) | 8 |
| Betriebstemperaturbereich (°C) 0 to 70 |
| Gehäusemenge | Träger 75 | TUBE |
Merkmale von SN75LVDS9637
- Meets or Exceeds the Requirements of ANSI TIA/EIA-644 Standard
- Operates With a Single 3.3-V Supply
- Designed for Signaling Rate of up to 155 Mbps
- Differential Input Thresholds ±100 mV Max
- Low-Voltage TTL (LVTTL) Logic Output Levels
- Open-Circuit Fail Safe
- Characterized For Operation From 0&dg;C to 70°C
Beschreibung von SN75LVDS9637
The SN75LVDS32 and SN75LVDS9637 are differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100 mV allow operation with a differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.
The intended application of these devices and signaling technique is both point-to-point and multidrop (one
driver and multiple receivers) data transmission over controlled impedance media of approximately 100 
. The
transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance
of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the
environment.
The SN75LVDS32 and SN75LVDS9637 are characterized for operation from 0°C to 70°C.