Gehäuseinformationen
| Gehäuse | Pins VQFN (RGY) | 20 |
| Betriebstemperaturbereich (°C) -55 to 125 |
| Gehäusemenge | Träger 250 | SMALL T&R |
Merkmale von TPS40170-EP
- Wide-Input Voltage Range from 4.5 V to 60 V
- 600-mV Reference Voltage With 1% Accuracy
- Programmable UVLO and Hysteresis
- Voltage-Mode Control With Voltage Feed-Forward
- Programmable Frequency Between 100 kHz and 600 kHz
- Bidirectional Frequency Synchronization With Master/Slave Option
- Low-Side FET Sensing Overcurrent Protection and High-Side FET Sensing
Short-Circuit Protection With Integrated Thermal Compensation - Programmable Closed-Loop Soft-Start
- Supports Pre-Biased Outputs
- Thermal Shutdown at 165°C With Hysteresis
- Voltage Tracking
- Power Good
- ENABLE With 1-µA Low-Current Shutdown
- 8-V and 3.3-V LDO Output
- Integrated Bootstrap Diode
- 20-Pin 3.5-mm × 4.5-mm QFN (RGY) Package
Beschreibung von TPS40170-EP
TPS40170 is a full-featured, synchronous PWM buck controller that operates at an input voltage between 4.5 V and 60 V and is optimized for high-power-density, high-reliability dc-dc converter applications. The controller implements voltage-mode control with input-voltage feed-forward compensation that enables instant response to an input voltage change. The switching frequency is programmable from 100 kHz to 600 kHz.
The TPS40170 has a complete set of system protection and monitoring features such as programmable UVLO, programmable overcurrent protection (OCP) by sensing the low-side FET, selectable short-circuit protection (SCP) by sensing the high-side FET, and thermal shutdown. The ENABLE pin allows for system shutdown in a low-current (1-µA typical) mode. The controller supports pre-biased output, provides an open-drain PGOOD signal, and has closed-loop soft-start, output-voltage tracking, and adaptive dead-time control.
TPS40170 provides accurate output-voltage regulation within 1% accuracy. Additionally, the controller implements a novel scheme of bidirectional synchronization with one controller acting as the master and other downstream controllers acting as slaves, synchronized to the master in-phase or 180° out-of-phase. Slave controllers can be synchronized to an external clock within ±30% of the free-running switching frequency.