Startseite Energiemanagement Mehrkanal-ICs (PMICs)
Startseite
Energiemanagement
Mehrkanal-ICs (PMICs)

TPS51116

AKTIV

Vollständiger synchroner Abwärtsregler für DDR-, DDR2-, DDR3-, DDR3L-, LPDDR3- und DDR4-Stromversorg

Jetzt bestellen
Datenblatt

TPS51116

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

Vin (min) (V) 3 Vin (max) (V) 28 Vout (min) (V) 0.75 Vout (max) (V) 3 Features Complete Solution, Shutdown Pin for S3 Iq (typ) (mA) 0.8 Rating Catalog Operating temperature range (°C) -40 to 85 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
Vin (min) (V) 3 Vin (max) (V) 28 Vout (min) (V) 0.75 Vout (max) (V) 3 Features Complete Solution, Shutdown Pin for S3 Iq (typ) (mA) 0.8 Rating Catalog Operating temperature range (°C) -40 to 85 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
HTSSOP (PWP) 20 41.6 mm² 6.5 x 6.4 VQFN (RGE) 24 16 mm² 4 x 4
  • Synchronous Buck Controller (VDDQ)
    • Wide-Input Voltage Range: 3.0-V to 28-V
    • D−CAP™ Mode with 100-ns Load Step Response
    • Current Mode Option Supports Ceramic Output Capacitors
    • Supports Soft-Off in S4/S5 States
    • Current Sensing from RDS(on) or Resistor
    • 2.5-V (DDR), 1.8-V (DDR2), Adjustable to
      1.5-V (DDR3), 1.35-V (DDR3L), 1.2-V (LPDDR3 and DDR4) or
      Output Range 0.75-V to 3.0-V
    • Equipped with Powergood, Overvoltage Protection and Undervoltage Protection
  • 3-A LDO (VTT), Buffered Reference (VREF)
    • Capable to Sink and Source 3 A
    • LDO Input Available to Optimize Power Losses
    • Requires only 20-µF Ceramic Output Capacitor
    • Buffered Low Noise 10-mA VREF Output
    • Accuracy ±20 mV for both VREF and VTT
    • Supports High-Z in S3 and Soft-Off in S4/S5
    • Thermal Shutdown
  • Synchronous Buck Controller (VDDQ)
    • Wide-Input Voltage Range: 3.0-V to 28-V
    • D−CAP™ Mode with 100-ns Load Step Response
    • Current Mode Option Supports Ceramic Output Capacitors
    • Supports Soft-Off in S4/S5 States
    • Current Sensing from RDS(on) or Resistor
    • 2.5-V (DDR), 1.8-V (DDR2), Adjustable to
      1.5-V (DDR3), 1.35-V (DDR3L), 1.2-V (LPDDR3 and DDR4) or
      Output Range 0.75-V to 3.0-V
    • Equipped with Powergood, Overvoltage Protection and Undervoltage Protection
  • 3-A LDO (VTT), Buffered Reference (VREF)
    • Capable to Sink and Source 3 A
    • LDO Input Available to Optimize Power Losses
    • Requires only 20-µF Ceramic Output Capacitor
    • Buffered Low Noise 10-mA VREF Output
    • Accuracy ±20 mV for both VREF and VTT
    • Supports High-Z in S3 and Soft-Off in S4/S5
    • Thermal Shutdown

The TPS51116 provides a complete power supply for DDR/SSTL-2, DDR2/SSTL-18, DDR3/SSTL-15, DDR3L, LPDDR3 and DDR4 memory systems. It integrates a synchronous buck controller with a 3-A sink/source tracking linear regulator and buffered low noise reference. The device offers the lowest total solution cost in systems where space is at a premium. The synchronous controller runs fixed 400-kHz, pseudo-constant frequency PWM with an adaptive on-time control that can be configured in D-CAP™ Mode for ease of use and fastest transient response or in current mode to support ceramic output capacitors. The 3-A sink/source LDO maintains fast transient response only requiring 20-µF (2 × 10 µF) of ceramic output capacitance. In addition, the LDO supply input is available externally to significantly reduce the total power losses. The device supports all of the sleep state controls placing VTT at high-Z in S3 (suspend to RAM) and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5 (suspend to disk). The device has all of the protection features including thermal shutdown and is offered in both a 20-pin HTSSOP PowerPAD™ package and 24-pin 4 × 4 QFN.

The TPS51116 provides a complete power supply for DDR/SSTL-2, DDR2/SSTL-18, DDR3/SSTL-15, DDR3L, LPDDR3 and DDR4 memory systems. It integrates a synchronous buck controller with a 3-A sink/source tracking linear regulator and buffered low noise reference. The device offers the lowest total solution cost in systems where space is at a premium. The synchronous controller runs fixed 400-kHz, pseudo-constant frequency PWM with an adaptive on-time control that can be configured in D-CAP™ Mode for ease of use and fastest transient response or in current mode to support ceramic output capacitors. The 3-A sink/source LDO maintains fast transient response only requiring 20-µF (2 × 10 µF) of ceramic output capacitance. In addition, the LDO supply input is available externally to significantly reduce the total power losses. The device supports all of the sleep state controls placing VTT at high-Z in S3 (suspend to RAM) and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5 (suspend to disk). The device has all of the protection features including thermal shutdown and is offered in both a 20-pin HTSSOP PowerPAD™ package and 24-pin 4 × 4 QFN.
open-in-new Andere Mehrkanal-ICs (PMICs) suchen
Herunterladen Video mit Transkript ansehen Video

Technische Dokumentation

star =Von TI ausgewählte Top-Empfehlungen für dieses Produkt
Keine Ergebnisse gefunden. Bitte geben Sie einen anderen Begriff ein und versuchen Sie es erneut.
Alle anzeigen 18
Typ Titel Datum
* Data sheet TPS51116 Complete DDR, DDR2, DDR3, DDR3L, LPDDR3 and DDR4 Power Solution Synchronous Buck Controller, 3-A LDO, Buffered Reference datasheet (Rev. J) PDF | HTML 16 Nov 2017
Analog Design Journal Control-Mode Quick Reference Guide (Rev. B) PDF | HTML 29 Aug 2023
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 09 Jul 2020
Selection guide Power Management Guide 2018 (Rev. R) 25 Jun 2018
Technical article Design advantage of D-CAP control topology PDF | HTML 13 Apr 2017
Technical article D-CAP3 – A sequel better than the original PDF | HTML 07 Mai 2015
More literature Computing DDR DC-DC Power Solutions 22 Aug 2012
Application note Intel Core i3, i5, i7 [Arrandale] Reference Design 21 Jul 2010
Application note Intel EP80579 Tolopai System-on-Chip Reference Design 21 Jul 2010
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs 28 Apr 2010
Application note Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices 20 Apr 2010
Application note Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) 31 Mär 2010
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) 26 Mär 2010
Application note Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs 26 Mär 2010
Application note TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers 26 Mär 2010
User guide Using the TPS51116 (Rev. A) 12 Nov 2008
Application note Cyclone™ III FPGA Starter Kit Power Reference Design 27 Mär 2008
Application note DDR2 Power Solutions for Notebooks 24 Mai 2004

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

TPS51116EVM-001 — TPS51116 Speicher-Leistungslösung, Synchron-Abwärts-Controller-Evaluierungsmodul

The TPS51116EVM evaluation module (EVM) is a dual-output converter for DDR and DDRII memory modules. It uses a 10 A synchronous buck converter to provide the core voltage (VDDQ) for DDR memory modules. The EVM is designed to use a 4.5 V to 28 V supply voltage and a 4.75 V to (...)

Benutzerhandbuch: PDF
Nicht verfügbar auf TI.com
Simulationsmodell

TPS51116 PSpice Transient Model (Rev. B)

SLIM076B.ZIP (101 KB) - PSpice Model
Herunterladen
Simulationsmodell

TPS51116 TINA-TI Transient Reference Design

SLUM166.TSC (224 KB) - TINA-TI Reference Design
Herunterladen
Simulationsmodell

TPS51116 TINA-TI Transient Spice Model

SLUM167.ZIP (58 KB) - TINA-TI Spice Model
Herunterladen
Referenzdesigns

PMP1516 — Komplette Stromversorgungslösung für DDR- oder DDR2-Speicheranwendungen

This DDR reference design provides a VDDQ of 2.5V @ 6A and a VTT of 1.25V. The 2.5V sync buck converter achieves an efficiency of 92% while the 1.25V minimizes area by implementing a built-in LDO and has excellent tracking performance.
Test report: PDF
Schaltplan: PDF
Referenzdesigns

PMP2543 — Referenzdesign für Power-Management mit Altera Cyclone III FPGA

The Cyclone III power management design is a complete, non-isolated power solution and provides all 5 required rails for powering the FPGA. The design also includes complete power solutions for DDR Memory VTT and VDDQ rails and USB power. This design is optimized to power the Altera 3C25F324 (...)
Test report: PDF
Schaltplan: PDF
Gehäuse Pins Herunterladen
HTSSOP (PWP) 20 Optionen anzeigen
VQFN (RGE) 24 Optionen anzeigen
Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

Bestellen & Qualität

Beinhaltete Information:
  • RoHS
  • REACH
  • Bausteinkennzeichnung
  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
  • Werksstandort
  • Montagestandort

Empfohlene Produkte können Parameter, Evaluierungsmodule oder Referenzdesigns zu diesem TI-Produkt beinhalten.

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Alle Forenthemen auf Englisch anzeigen

Inhalte werden ohne Gewähr von TI und der Community bereitgestellt. Sie stellen keine Spezifikationen von TI dar. Siehe Nutzungsbedingungen.

Bei Fragen zu den Themen Qualität, Gehäuse oder Bestellung von TI-Produkten siehe TI-Support. ​​​​​​​​​​​​​​

Videos