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Generadores de señal de reloj

CDCEL937-Q1

ACTIVO

Sintetizador de reloj VCXO programable de 3 PLL con salidas LVCMOS de 1,8 V de catálogo automotriz

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CDCEL937-Q1

ACTIVO
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Detalles del producto

Function Clock generator, Spread-spectrum clock generator Number of outputs 7 Output frequency (max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 1.8 Input type LVCMOS, XTAL Output type LVCMOS Operating temperature range (°C) -40 to 125 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Automotive
Function Clock generator, Spread-spectrum clock generator Number of outputs 7 Output frequency (max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 1.8 Input type LVCMOS, XTAL Output type LVCMOS Operating temperature range (°C) -40 to 125 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Automotive
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • In-System Programmability and EEPROM
    • Serial Programmable Volatile Register
    • Nonvolatile EEPROM to Store Customer Setting
  • Flexible Input Clocking Concept
    • External Crystal: 8 MHz to 32 MHz
    • On-Chip VCXO: Pull Range ±150 ppm
    • Single-Ended LVCMOS up to 160 MHz
  • Free Selectable Output Frequency up to 230  MHz
  • Low-Noise PLL Core
    • Integrated PLL Loop Filter Components
    • Low Period Jitter (Typical 60 ps)
  • Separate Output Supply Pins
    • CDCE937-Q1: 3.3 V and 2.5 V
    • CDCEL937-Q1: 1.8 V
  • Flexible Clock Driver
    • Three User-Definable Control Inputs [S0/S1/S2]; for Example: SSC Selection, Frequency Switching, Output Enable or Power Down
    • Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth™, WLAN, Ethernet™, and GPS
    • Generates Common Clock Frequencies Used With TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC Modulation
    • Enables 0-PPM Clock Generation
  • 1.8-V Device Power Supply
  • Wide Temperature Range –40°C to 125°C
  • Packaged in TSSOP
  • Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)
  • APPLICATIONS
    • Clusters
    • Head Units
    • Navigation Systems
    • Advanced Driver Assistance Systems (ADAS)

All other trademarks are the property of their respective owners.
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • In-System Programmability and EEPROM
    • Serial Programmable Volatile Register
    • Nonvolatile EEPROM to Store Customer Setting
  • Flexible Input Clocking Concept
    • External Crystal: 8 MHz to 32 MHz
    • On-Chip VCXO: Pull Range ±150 ppm
    • Single-Ended LVCMOS up to 160 MHz
  • Free Selectable Output Frequency up to 230  MHz
  • Low-Noise PLL Core
    • Integrated PLL Loop Filter Components
    • Low Period Jitter (Typical 60 ps)
  • Separate Output Supply Pins
    • CDCE937-Q1: 3.3 V and 2.5 V
    • CDCEL937-Q1: 1.8 V
  • Flexible Clock Driver
    • Three User-Definable Control Inputs [S0/S1/S2]; for Example: SSC Selection, Frequency Switching, Output Enable or Power Down
    • Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth™, WLAN, Ethernet™, and GPS
    • Generates Common Clock Frequencies Used With TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC Modulation
    • Enables 0-PPM Clock Generation
  • 1.8-V Device Power Supply
  • Wide Temperature Range –40°C to 125°C
  • Packaged in TSSOP
  • Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)
  • APPLICATIONS
    • Clusters
    • Head Units
    • Navigation Systems
    • Advanced Driver Assistance Systems (ADAS)

All other trademarks are the property of their respective owners.

The CDCE937-Q1 and CDCEL937-Q1 devices are modular, phase-locked loop (PLL) based programmable clock synthesizers. These devices provide flexible and programmable options, such as output clocks, input signals, and control pins, so that the user can configure the CDCEx937-Q1 for their own specifications.

The CDCEx937-Q1 generates up to seven output clocks from a single input frequency to enable both board space and cost savings. Additionally, with multiple outputs, the clock generator can replace multiple crystals with one clock generator. This makes the device well-suited for head unit and telematics applications in infotainment and camera systems in ADAS as these platforms are evolving into smaller and more cost effective systems.

Furthermore, each output can be programmed in-system for any clock frequency up to 230 MHz through the integrated, configurable PLL. The PLL also supports spread-spectrum clocking (SSC) with programmable down and center spread. This provides better electromagnetic interference (EMI) performance to enable customers to pass industry standards such as CISPR-25.

Customization of frequency programming and SSC are accessed using three user-defined control pins. This eliminates the additional interface requirement to control the clock. Specific power-up and power-down sequences can also be defined to the userΩs needs.

The CDCE937-Q1 and CDCEL937-Q1 devices are modular, phase-locked loop (PLL) based programmable clock synthesizers. These devices provide flexible and programmable options, such as output clocks, input signals, and control pins, so that the user can configure the CDCEx937-Q1 for their own specifications.

The CDCEx937-Q1 generates up to seven output clocks from a single input frequency to enable both board space and cost savings. Additionally, with multiple outputs, the clock generator can replace multiple crystals with one clock generator. This makes the device well-suited for head unit and telematics applications in infotainment and camera systems in ADAS as these platforms are evolving into smaller and more cost effective systems.

Furthermore, each output can be programmed in-system for any clock frequency up to 230 MHz through the integrated, configurable PLL. The PLL also supports spread-spectrum clocking (SSC) with programmable down and center spread. This provides better electromagnetic interference (EMI) performance to enable customers to pass industry standards such as CISPR-25.

Customization of frequency programming and SSC are accessed using three user-defined control pins. This eliminates the additional interface requirement to control the clock. Specific power-up and power-down sequences can also be defined to the userΩs needs.
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Documentación técnica

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Tipo Título Fecha
* Data sheet CDCEx937-Q1 Programmable 3-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V LVCMOS Outputs datasheet (Rev. C) PDF | HTML 16 dic 2016
Application note Crystal or Crystal Oscillator Replacement with Silicon Devices 18 jun 2014
Application note VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) 23 abr 2012
User guide CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) 22 nov 2010
Application note General I2C / EEPROM usage for the CDCE(L)9xx family 26 ene 2010
Application note Troubleshooting I2C Bus Protocol 19 oct 2009
Application note Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 23 sep 2009
Application note Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency 31 mar 2008

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CLOCK-TREE-ARCHITECT — Software de programación de diseño de árbol de reloj

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TSSOP (PW) 20 Ver opciones
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