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Sincronizadores de red de reloj

LMK5C23208A

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Sincronizador de red con dos DPLL, tres APLL, dos entradas y ocho salidas con JESD204B/C y VCO basad

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LMK5C23208A

ACTIVO
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Detalles del producto

Function Clock network synchronizer Number of outputs 8 Output type CML, LVCMOS, LVDS, LVPECL RMS jitter (fs) 50 Features JESD204B Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 3000 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Operating temperature range (°C) -40 to 85 Number of input channels 2
Function Clock network synchronizer Number of outputs 8 Output type CML, LVCMOS, LVDS, LVPECL RMS jitter (fs) 50 Features JESD204B Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 3000 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Operating temperature range (°C) -40 to 85 Number of input channels 2
VQFN (RGC) 64 81 mm² (9 mm × 9 mm)
  • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks
    • 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
    • 50fs typical/ 62fs maximum RMS jitter at 245.76MHz

  • 2 high-performance Digital Phase Locked Loop (DPLL) with 3 Analog Phase Locked Loops (APLLs)

    • Programmable DPLL loop filter bandwidth from 1mHz to 4kHz
    • < 1ppt DCO frequency adjustment step size
  • 2 differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital Holdover and Hitless Switching
  • 8 differential outputs with programmable HSDS, AC-LVPECL, LVDS and HSCL formats
    • Up to 12 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT0_P/N, OUT1_P/N, GPIO1, and GPIO2 and 6 differential outputs on OUT3_P/N to OUT15_P/N
    • 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 6 compliant
  • I2C or 3-wire/4-wire SPI
  • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks
    • 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
    • 50fs typical/ 62fs maximum RMS jitter at 245.76MHz

  • 2 high-performance Digital Phase Locked Loop (DPLL) with 3 Analog Phase Locked Loops (APLLs)

    • Programmable DPLL loop filter bandwidth from 1mHz to 4kHz
    • < 1ppt DCO frequency adjustment step size
  • 2 differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital Holdover and Hitless Switching
  • 8 differential outputs with programmable HSDS, AC-LVPECL, LVDS and HSCL formats
    • Up to 12 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT0_P/N, OUT1_P/N, GPIO1, and GPIO2 and 6 differential outputs on OUT3_P/N to OUT15_P/N
    • 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 6 compliant
  • I2C or 3-wire/4-wire SPI

The LMK5C23208A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The device integrates two DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use.

APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology. The BAW APLL can generate 491.52MHz output clocks with 40fs typical / 60fs maximum RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 (conventional LC VCOs) provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.

The LMK5C23208A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The device integrates two DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use.

APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology. The BAW APLL can generate 491.52MHz output clocks with 40fs typical / 60fs maximum RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 (conventional LC VCOs) provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos LMK5C23208A 2-DPLL 3-APLL 2-IN 8-OUT Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications datasheet PDF | HTML 14/05/2025
Nota sobre la aplicación Termination Guidelines for Differential and Single-Ended Signals PDF | HTML 10/12/2025
Guía del usuario LMK5C23208A Programmer's Guide (Rev. A) PDF | HTML 17/11/2025
Nota sobre la aplicación Oscillator Power Considerations for PLL Devices PDF | HTML 30/10/2025

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