SN54SC4T125-SEP

ACTIVO

Convertidor de nivel de dirección fija de 4 bits con tolerancia a las radiaciones

Detalles del producto

Technology family SCxT Applications GPIO Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 0 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -16 IOL (max) (mA) -16 Supply current (max) (µA) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type TTL-Compatible CMOS Output type 3-State Rating Space Operating temperature range (°C) -55 to 125
Technology family SCxT Applications GPIO Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 0 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -16 IOL (max) (mA) -16 Supply current (max) (µA) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type TTL-Compatible CMOS Output type 3-State Rating Space Operating temperature range (°C) -55 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4
  • VID V62/23631-01XE

  • Radiation Tolerant

    • Single Event Latch-Up (SEL) immune up to 43 MeV-cm 2/mg at 125°C

    • Total Ionizing Does (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30 krad(Si)

    • Single Event Transient (SET) characterized up to LET = 43 MeV-cm 2/mg

  • Wide operating range of 1.2 V to 5.5 V

  • Single-supply voltage translator:

    • Up translation:

      • 1.2 V to 1.8 V

      • 1.5 V to 2.5 V

      • 1.8 V to 3.3 V

      • 3.3 V to 5.0 V

    • Down translation:

      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17
  • Space Enhanced Plastic

    • Controlled baseline

    • Au bondwire and NiPdAu lead finish

    • Meets NASA ASTM E595 outgassing specification

    • One fabrication, assembly, and test site

    • Extended product life cycle

    • Product traceability

  • VID V62/23631-01XE

  • Radiation Tolerant

    • Single Event Latch-Up (SEL) immune up to 43 MeV-cm 2/mg at 125°C

    • Total Ionizing Does (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30 krad(Si)

    • Single Event Transient (SET) characterized up to LET = 43 MeV-cm 2/mg

  • Wide operating range of 1.2 V to 5.5 V

  • Single-supply voltage translator:

    • Up translation:

      • 1.2 V to 1.8 V

      • 1.5 V to 2.5 V

      • 1.8 V to 3.3 V

      • 3.3 V to 5.0 V

    • Down translation:

      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17
  • Space Enhanced Plastic

    • Controlled baseline

    • Au bondwire and NiPdAu lead finish

    • Meets NASA ASTM E595 outgassing specification

    • One fabrication, assembly, and test site

    • Extended product life cycle

    • Product traceability

The SN54SC4T125-SEP contains four independent buffers with 3-state outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a high impedance (Hi-Z) state by applying a HIGH on the OE pin. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN54SC4T125-SEP contains four independent buffers with 3-state outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a high impedance (Hi-Z) state by applying a HIGH on the OE pin. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

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Documentación técnica

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* Data sheet SN54SC4T125-SEP Radiation Tolerant, Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter datasheet PDF | HTML 15 nov 2023
* Radiation & reliability report SN54SC4T125-SEP Single Event Effects Report PDF | HTML 05 dic 2023
* Radiation & reliability report SN54SC4T125-SEP Total Ionizing Dose (TID) Report PDF | HTML 01 dic 2023
* Radiation & reliability report SN54SC4T125-SEP Production Flow and Reliability Report PDF | HTML 09 nov 2023
Application note Understanding Transient Drive Strength vs. DC Drive Strength in CMOS Output Buffers PDF | HTML 14 may 2024

Diseño y desarrollo

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Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

Guía del usuario: PDF | HTML
Paquete Pasadores Descargar
TSSOP (PW) 14 Ver opciones

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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