SN74AVC4T245

ACTIVO

Transceptor de bus de automoción de 4 bits y doble alimentación con cambio de nivel de tensión confi

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SN74AXC4T245 ACTIVO Transceptor de bus de alimentación doble de 4 bits Pin-to-pin upgrade with a wider voltage range and improved performance

Detalles del producto

Technology family AVC Applications JTAG, SPI, UART Bits (#) 4 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 125
Technology family AVC Applications JTAG, SPI, UART Bits (#) 4 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (D) 16 59.4 mm² 9.9 x 6 SOT-23-THN (DYY) 16 8.4 mm² 4.2 x 2 TSSOP (PW) 16 32 mm² 5 x 6.4 TVSOP (DGV) 16 23.04 mm² 3.6 x 6.4 UQFN (RSV) 16 4.68 mm² 2.6 x 1.8 VQFN (RGY) 16 14 mm² 4 x 3.5 WQFN (BQB) 16 8.75 mm² 3.5 x 2.5
  • Control inputs VIH/VIL levels are referenced to VCCA voltage
  • Fully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply range
  • I/Os Are 4.6V tolerant
  • Ioff supports partial power-down-mode operation
  • Maximum data rates:
    • 380Mbps (1.8V to 3.3V translation)
    • 200Mbps (< 1.8V to 3.3V translation)
    • 200Mbps (translate to 2.5V or 1.8V)
    • 150Mbps (translate to 1.5V)
    • 100Mbps (translate to 1.2V)
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 8000V Human-Body Model (A114-A)
    • 150V Machine Model (A115-A)
    • 1000V Charged-Device Model (C101)
  • Control inputs VIH/VIL levels are referenced to VCCA voltage
  • Fully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply range
  • I/Os Are 4.6V tolerant
  • Ioff supports partial power-down-mode operation
  • Maximum data rates:
    • 380Mbps (1.8V to 3.3V translation)
    • 200Mbps (< 1.8V to 3.3V translation)
    • 200Mbps (translate to 2.5V or 1.8V)
    • 150Mbps (translate to 1.5V)
    • 100Mbps (translate to 1.2V)
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 8000V Human-Body Model (A114-A)
    • 150V Machine Model (A115-A)
    • 1000V Charged-Device Model (C101)

This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. The SN74AVC4T245 is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC4T245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC4T245 device is designed so that VCCA supplies the control pins (1DIR, 2DIR, 1 OE, and 2 OE).

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

To put the device in the high-impedance state during power up or power down, tie OE to VCC through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.

This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. The SN74AVC4T245 is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC4T245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC4T245 device is designed so that VCCA supplies the control pins (1DIR, 2DIR, 1 OE, and 2 OE).

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

To put the device in the high-impedance state during power up or power down, tie OE to VCC through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.

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Documentación técnica

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Tipo Título Fecha
* Data sheet SN74AVC4T245 Dual-Bit Bus Transceiver with Configurable Voltage Translation and 3-State Outputs datasheet (Rev. H) PDF | HTML 20 mar 2024
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 oct 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 jul 2024
EVM User's guide Generic AVC and LVC Direction Controlled Translation EVM (Rev. B) 30 jul 2021
EVM User's guide AXC Small-Package Evaluation Module User's Guide (Rev. A) PDF | HTML 12 jul 2021
Selection guide Voltage Translation Buying Guide (Rev. A) 15 abr 2021
Technical article Benefits of using Sub-1 GHz connectivity for grid asset monitoring, protection and PDF | HTML 28 may 2020
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 30 abr 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
More literature LCD Module Interface Application Clip 09 may 2003
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 20 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 07 jul 1999
Application note AVC Logic Family Technology and Applications (Rev. A) 26 ago 1998

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

Guía del usuario: PDF | HTML
Placa de evaluación

14-24-NL-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados sin conductores de 14 a 24 pine

14-24-NL-LOGIC-EVM es un módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo lógico o de traducción que tenga un encapsulado BQA, BQB, RGY, RSV, RJW o RHL de 14 a 24 pines.

Guía del usuario: PDF | HTML
Placa de evaluación

AVCLVCDIRCNTRL-EVM — EVM genérico para dispositivo de traducción bidireccional controlado por dirección compatible con AV

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

Guía del usuario: PDF
Kit de desarrollo

EVMK2GX — Módulo de evaluación 66AK2Gx de 1 GHz

The EVMK2GX (also known as "K2G") 1GHz evaluation module (EVM) enables developers to immediately start evaluating the 66AK2Gx processor family, and to accelerate the development of audio, industrial motor control, smart grid protection and other high reliability, real-time compute intensive (...)

Guía del usuario: PDF
Modelo de simulación

SN74AVC4T245 IBIS Model (Rev. B)

SCEM503B.ZIP (68 KB) - IBIS Model

Muchos diseños de referencia de TI incluyen SN74AVC4T245

Utilice nuestra herramienta de selección de diseños de referencia para revisar e identificar los diseños que mejor se adaptan a su aplicación y parámetros.

Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (D) 16 Ultra Librarian
SOT-23-THN (DYY) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
TVSOP (DGV) 16 Ultra Librarian
UQFN (RSV) 16 Ultra Librarian
VQFN (RGY) 16 Ultra Librarian
WQFN (BQB) 16 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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