The TPS650830 is a single-chip solution Power Management IC designed specifically for the latest Intel Processors targeted for Tablets, Ultrabooks, and Notebooks with NVDC or non-NVDC power architectures, using 2S, 3S, or 4S Lithium-Ion battery packs.
The TPS650830 is used for Volume systems with the low voltage rails merged for the smallest footprint and lowest cost system power solution.
The TPS650830 can provide the complete power solution based on the Intel Reference Designs. Five highly efficient step-down voltage regulators (VRs) and a sink/source LDO, are used along with power-up sequence logic managing external load switches to provide the proper power rails, sequencing, and protection - including DDR3 and DDR4 memory power. The regulators support dynamic voltage scaling (DVS) for maximum efficiency including Connected Standby. The high frequency voltage regulators use small inductors and capacitors to achieve a small solution size. Output power is adjustable on four VR controllers. An I2C interface allows simple control by the embedded controller (EC). Each version is available in a 7x7 NFBGA package and a 9x9 NFBGA package. The 7x7 NFBGA package can be used in Type 4 PCB boards for the smallest area implementation. The 9x9 NFBGA package can be used in Type 3 and Type 4 PCB boards allowing to minimize cost and area.
For the Skylake and Kabylake Power Map implementation, the five PMIC voltage regulators and LDO1 are assigned with the low-voltage rails merged or split according to the configuration. For the Volume (merged low voltage rails) configuration six external load switches are controlled and monitored by using six powergood comparator logic blocs.
| Documentación principal | Tipo | Título | Opciones de formato | Descargar la versión más reciente en inglés | Fecha |
|---|---|---|---|---|---|
| * | Hoja de datos | TPS650830 Simple and Flexible Wide Input Voltage PMU for Mobile Computers datasheet (Rev. A) | PDF | HTML | 5/07/2016 | |
| Nota sobre la aplicación | Optimizing Resistor Dividers at a Comparator (Rev. B) | PDF | HTML | 30/04/2021 | ||
| Nota sobre la aplicación | Basic Calculation of a Buck Converter's Power Stage (Rev. B) | PDF | HTML | 17/08/2015 | ||
| Artículo técnico | An efficient, flexible, single-chip power solution for Skylake processors | PDF | HTML | 1/06/2015 | ||
| Guía de diseño | TPS65083x Design Guide | 24/02/2015 | |||
| Analog Design Journal | Controlling switch-node ringing in synchronous buck converters | 26/04/2012 | |||
| Nota sobre la aplicación | Ringing Reduction Techniques for NexFET High Performance MOSFETs | 16/11/2011 |
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
TPS650830EVM-095 is an Evaluation Module, (EVM) board for the TPS650830. This EVM provides a platform for engineers to evaluate, test, and explore the TPS650830 in a real world application use. All of the sequencing and functionality required for the processor and system is demonstrated on this (...)
| Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
|---|---|---|
| NFBGA (ZAJ) | 168 | Ultra Librarian |
| NFBGA (ZCG) | 159 | Ultra Librarian |
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