LMG3660R025
ゲート ドライバ内蔵、650V、25mΩ、TOLT パッケージ封止、GaN FET
LMG3660R025
- 650V 25mΩ GaN power FET with integrated gate driver
- >200V/ns FET hold-off
- 10V/ns to 80V/ns slew rate for optimization of switching performance and EMI mitigation
- Operates with supply pin and input logic pin voltage range from 9V to 26V
- Robust protection
- Cycle-by-cycle overcurrent and latched short-circuit protection with <300ns response
- Withstands 720V surge while hard-switching
- Self-protection from internal overtemperature and UVLO monitoring
- Advanced power management
- LMG3666R025 includes zero-voltage detection (ZVD) feature that facilitates soft-switching converters and an adjustable turn-off slew rate from 10V/ns to full speed.
- LMG3667R025 includes zero-current detection (ZCD) feature that facilitates soft-switching converters and an adjustable turn-off slew rate from 10V/ns to full speed.
- Top-side cooled 10.1mm × 15.2mm TOLT package separates electrical and thermal paths for lowest power loop inductance
The LMG366xR025 GaN FET with integrated driver and protection is targeted at switch-mode power converters and enables designers to achieve new levels of power density and efficiency.
Adjustable gate driver strength allows the control of turn-on and maximum turn-off slew rates independently, which can be used to actively control EMI and optimize switching performance. Turn on slew rate varies from 10V/ns to 80V/ns, while the turn off slew rate control is available only in LMG3666R025 and LMG3667R025. The turn off slew rate can be limited from 10V/ns to a maximum based on the magnitude of load current. Protection features include under-voltage lockout (UVLO), cycle-by-cycle overcurrent limit, and short-circuit and overtemperature protection. The LMG3661R025 provides a 5V LDO output on LDO5V pin that powers external digital isolators. The LMG3666R025 includes the zero-voltage detection (ZVD) feature which provides a pulse output from the ZVD pin when zero-voltage switching is realized. The LMG3667R025 includes the zero-current detection (ZCD) feature that sets the ZCD pin high when the drain-to-source current is negative and transitions to low upon detecting the zero-crossing point.
技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | LMG366xR025 650V 25 mΩ GaN FET With Integrated Driver and Protection データシート | PDF | HTML | 2026年 3月 4日 |
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