제품 상세 정보

Configuration 4:1 Number of channels 2 Power supply voltage - single (V) 3.3, 5, 12, 16, 20 Power supply voltage - dual (V) +/-10, +/-2.5, +/-5 Protocols Analog Ron (typ) (Ω) 125 CON (typ) (pF) 18 ON-state leakage current (max) (µA) 0.3 Supply current (typ) (µA) 0.04 Bandwidth (MHz) 25 Operating temperature range (°C) -55 to 125 Features Break-before-make Input/output continuous current (max) (mA) 10 Rating Military Drain supply voltage (max) (V) 20 Supply voltage (max) (V) 20 Negative rail supply voltage (max) (V) 0
Configuration 4:1 Number of channels 2 Power supply voltage - single (V) 3.3, 5, 12, 16, 20 Power supply voltage - dual (V) +/-10, +/-2.5, +/-5 Protocols Analog Ron (typ) (Ω) 125 CON (typ) (pF) 18 ON-state leakage current (max) (µA) 0.3 Supply current (typ) (µA) 0.04 Bandwidth (MHz) 25 Operating temperature range (°C) -55 to 125 Features Break-before-make Input/output continuous current (max) (mA) 10 Rating Military Drain supply voltage (max) (V) 20 Supply voltage (max) (V) 20 Negative rail supply voltage (max) (V) 0
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • Wide range of digital and analog signal levels:
    • Digital: 3 V to 20 V
    • Analog: ≤ 20 V P-P
  • Low ON resistance, 125 Ω (typical) over 15 V P-P signal input range for V DD – V EE = 18 V
  • High OFF resistance, channel leakage of ±100 pA (typical) at V DD – V EE = 18 V
  • Logic-level conversion for digital addressing signals of 3 V to 20 V (V DD – V SS = 3 V to 20 V) to switch analog signals to 20 V P-P (V DD – V EE = 20 V) matched switch characteristics, r ON = 5 Ω (typical) for V DD – V EE = 15 V very low quiescent power dissipation under all digital-control input and supply conditions, 0.2 µW (typical) at V DD – V SS = V DD – V EE = 10 V
  • Binary address decoding on chip
  • 5 V, 10 V, and 15 V parametric ratings
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package temperature range, 100 nA at 18 V and 25°C
  • Break-before-make switching eliminates channel overlap
  • Wide range of digital and analog signal levels:
    • Digital: 3 V to 20 V
    • Analog: ≤ 20 V P-P
  • Low ON resistance, 125 Ω (typical) over 15 V P-P signal input range for V DD – V EE = 18 V
  • High OFF resistance, channel leakage of ±100 pA (typical) at V DD – V EE = 18 V
  • Logic-level conversion for digital addressing signals of 3 V to 20 V (V DD – V SS = 3 V to 20 V) to switch analog signals to 20 V P-P (V DD – V EE = 20 V) matched switch characteristics, r ON = 5 Ω (typical) for V DD – V EE = 15 V very low quiescent power dissipation under all digital-control input and supply conditions, 0.2 µW (typical) at V DD – V SS = V DD – V EE = 10 V
  • Binary address decoding on chip
  • 5 V, 10 V, and 15 V parametric ratings
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package temperature range, 100 nA at 18 V and 25°C
  • Break-before-make switching eliminates channel overlap

The CD405xB analog multiplexers and demultiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. These multiplexer circuits dissipate extremely low quiescent power over the full V DD – V SS and V DD – V EE supply-voltage ranges, independent of the logic state of the control signals.

The CD405xB analog multiplexers and demultiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. These multiplexer circuits dissipate extremely low quiescent power over the full V DD – V SS and V DD – V EE supply-voltage ranges, independent of the logic state of the control signals.

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CD4052B 활성 20V, 4:1, 2채널 범용 멀티플렉서 Commercial version

기술 자료

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10개 모두 보기
유형 직함 날짜
* Data sheet CD405xB CMOS Single 8-Channel Analog Multiplexer or DemultiplexerWith Logic-Level Conversion datasheet (Rev. L) PDF | HTML 2023/09/05
* SMD CD4052B-MIL SMD 7901502EA 2016/06/21
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022/06/02
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021/12/01
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001/12/03

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CDIP (J) 16 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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