제품 상세 정보

Function Zero-delay Additive RMS jitter (typ) (fs) 200 Output frequency (max) (MHz) 100 Number of outputs 6 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 500 Operating temperature range (°C) 0 to 70 Rating Catalog Output type TTL Input type TTL
Function Zero-delay Additive RMS jitter (typ) (fs) 200 Output frequency (max) (MHz) 100 Number of outputs 6 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 500 Operating temperature range (°C) 0 to 70 Rating Catalog Output type TTL Input type TTL
SSOP (DB) 28 79.56 mm² 10.2 x 7.8
  • Low-Output Skew for Clock-Distribution and Clock-Generation Applications
  • Operates at 3.3-V VCC
  • Distributes One Clock Input to Six Outputs
  • One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency
  • No External RC Network Required
  • External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
  • Application for Synchronous DRAM, High-Speed Microprocessor
  • Negative-Edge-Triggered Clear for Half-Frequency Outputs
  • TTL-Compatible Inputs and Outputs
  • Outputs Drive 50- Parallel-Terminated Transmission Lines
  • State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • Packaged in Plastic 28-Pin Shrink Small Outline Package

EPIC-IIB is a trademark of Texas Instruments.

  • Low-Output Skew for Clock-Distribution and Clock-Generation Applications
  • Operates at 3.3-V VCC
  • Distributes One Clock Input to Six Outputs
  • One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency
  • No External RC Network Required
  • External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
  • Application for Synchronous DRAM, High-Speed Microprocessor
  • Negative-Edge-Triggered Clear for Half-Frequency Outputs
  • TTL-Compatible Inputs and Outputs
  • Outputs Drive 50- Parallel-Terminated Transmission Lines
  • State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • Packaged in Plastic 28-Pin Shrink Small Outline Package

EPIC-IIB is a trademark of Texas Instruments.

The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V VCC and is designed to drive a 50-W transmission line.

The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock (CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clock.

Output-enable (OE)\ is provided for output control. When OE\ is high, the outputs are in the high-impedance state. When OE\ is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass the PLL. TEST should be strapped to GND for normal operation.

Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC536 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of the select inputs, enabling the PLL via TEST, and upon enable of all outputs via OE\.

The CDC536 is characterized for operation from 0°C to 70°C.

The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V VCC and is designed to drive a 50-W transmission line.

The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock (CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clock.

Output-enable (OE)\ is provided for output control. When OE\ is high, the outputs are in the high-impedance state. When OE\ is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass the PLL. TEST should be strapped to GND for normal operation.

Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC536 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of the select inputs, enabling the PLL via TEST, and upon enable of all outputs via OE\.

The CDC536 is characterized for operation from 0°C to 70°C.

다운로드 스크립트와 함께 비디오 보기 동영상

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
2개 모두 보기
유형 직함 날짜
* Data sheet CDC536: 3.3-V PLL Clock Driver With 3-State Outputs datasheet (Rev. G) 2004/07/08
Application note Application and Design Considerations for CDC5xx Phase-Lock Loop Clock Drivers 1996/04/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 모델

CDC536 IBIS Model

SCAM018.ZIP (10 KB) - IBIS Model
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
패키지 CAD 기호, 풋프린트 및 3D 모델
SSOP (DB) 28 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상