제품 상세 정보

Function Ultra-low jitter clock generator Number of outputs 8 Output frequency (max) (MHz) 800 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type CML, LVCMOS, LVDS, LVPECL, XTAL Output type CML, HCSL, LVCMOS, LVDS, LVPECL Operating temperature range (°C) -40 to 85 Features I2C, Pin programmable, SPI Rating Catalog
Function Ultra-low jitter clock generator Number of outputs 8 Output frequency (max) (MHz) 800 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type CML, LVCMOS, LVDS, LVPECL, XTAL Output type CML, HCSL, LVCMOS, LVDS, LVPECL Operating temperature range (°C) -40 to 85 Features I2C, Pin programmable, SPI Rating Catalog
VQFN (RGZ) 48 49 mm² 7 x 7
  • Superior Performance with Low Power:
    • Low Noise Synthesizer (265 fs-rms Typical
      Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms
      Typical Jitter)
    • 0.5 W Typical Power Consumption
    • High Channel-to-Channel Isolation and
      Excellent PSRR
    • Device Performance Customizable Through
      Flexible 1.8 V, 2.5 V and 3.3 V Power
      Supplies, Allowing Mixed Output Voltages
  • Flexible Frequency Planning:
    • 4x Integer Down-divided Differential Clock
      Outputs Supporting LVPECL-like, CML, or
      LVDS-like Signaling
    • 4x Fractional or Integer Divided Differential
      Clock Outputs Supporting HCSL, LVDS-like
      Signaling, or Eight CMOS Outputs
    • Fractional Output Divider Achieve 0 ppm to < 1
      ppm Frequency Error and Eliminates need for
      Crystal Oscillators and Other Clock Generators
    • Output frequencies up to 800 MHz
  • Two Differential Inputs, XTAL Support, Ability for
    Smart Switching
  • SPI, I2C™, and Pin Programmable
  • Professional user GUI for Quick Design
    Turnaround
  • 7 × 7 mm 48-QFN package (RGZ)
  • –40 °C to 85 °C temperature range
  • Superior Performance with Low Power:
    • Low Noise Synthesizer (265 fs-rms Typical
      Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms
      Typical Jitter)
    • 0.5 W Typical Power Consumption
    • High Channel-to-Channel Isolation and
      Excellent PSRR
    • Device Performance Customizable Through
      Flexible 1.8 V, 2.5 V and 3.3 V Power
      Supplies, Allowing Mixed Output Voltages
  • Flexible Frequency Planning:
    • 4x Integer Down-divided Differential Clock
      Outputs Supporting LVPECL-like, CML, or
      LVDS-like Signaling
    • 4x Fractional or Integer Divided Differential
      Clock Outputs Supporting HCSL, LVDS-like
      Signaling, or Eight CMOS Outputs
    • Fractional Output Divider Achieve 0 ppm to < 1
      ppm Frequency Error and Eliminates need for
      Crystal Oscillators and Other Clock Generators
    • Output frequencies up to 800 MHz
  • Two Differential Inputs, XTAL Support, Ability for
    Smart Switching
  • SPI, I2C™, and Pin Programmable
  • Professional user GUI for Quick Design
    Turnaround
  • 7 × 7 mm 48-QFN package (RGZ)
  • –40 °C to 85 °C temperature range

The CDCM6208V1F is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208V1F also features an innovative fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208V1F can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins.

In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k – 20 MHz) or 20 ps-pp (unbound) on output using integer dividers and is between 50 to 220 ps-pp (10 k – 40 MHz) on outputs using fractional dividers depending on the prescaler output frequency.

In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k – 20 MHz) or 40 ps-pp on output using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The CDCM6208V1F is packaged in a small 48-pin 7 mm × 7 mm QFN package.

The CDCM6208V1F is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208V1F also features an innovative fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208V1F can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins.

In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k – 20 MHz) or 20 ps-pp (unbound) on output using integer dividers and is between 50 to 220 ps-pp (10 k – 40 MHz) on outputs using fractional dividers depending on the prescaler output frequency.

In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k – 20 MHz) or 40 ps-pp on output using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The CDCM6208V1F is packaged in a small 48-pin 7 mm × 7 mm QFN package.

다운로드 스크립트와 함께 비디오 보기 동영상

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
2개 모두 보기
유형 직함 날짜
* Data sheet CDCM6208V1F 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers datasheet PDF | HTML 2015/05/07
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 2024/04/30

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

설계 툴

CLOCK-TREE-ARCHITECT — 클록 트리 아키텍트 프로그래밍 소프트웨어

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
패키지 CAD 기호, 풋프린트 및 3D 모델
VQFN (RGZ) 48 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상