DS90CF364
- 20 to 65 MHz shift clock support
- Programmable Transmitter (DS90C363) strobe select (Rising or Falling edge strobe)
- Single 3.3V supply
- Chipset (TX + RX) power consumption < 250 mW (typ)
- Power-down mode (< 0.5 mW total)
- Single pixel per clock XGA (1024×768) ready
- Supports VGA, SVGA, XGA and higher addressability
- Up to 170 Megabyte/sec bandwidth
- Up to 1.3 Gbps throughput
- Narrow bus reduces cable size and cost
- 290 mV swing LVDS devices for low EMI
- PLL requires no external components
- Low profile 48-lead TSSOP package
- Falling edge data strobe Receiver
- Compatible with TIA/EIA-644 LVDS standard
- ESD rating > 7 kV
- Operating Temperature: −40°C to +85°C
All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments. TRI-STATE is a trademark of Texas Instruments.
The DS90C363 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF364 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 170 Mbyte/sec. The Transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The Transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge Transmitter will inter-operate with a Falling edge Receiver (DS90CF364) without any translation logic.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | DS90C363/F364 3.3V Prog LVDS Trnsmit 18Bit FPD 65MHz/LVDS Rcvr 18Bit FPD 85MHz datasheet (Rev. C) | 2013. 4. 12 | ||
| 애플리케이션 노트 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018. 11. 9 | |||
| 애플리케이션 노트 | How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) | 2018. 6. 29 | |||
| 애플리케이션 노트 | AN-1032 An Introduction to FPD-Link (Rev. C) | 2017. 8. 8 | |||
| 애플리케이션 노트 | Receiver Skew Margin for Channel Link I and FPD Link I Devices | PDF | HTML | 2016. 1. 13 | ||
| 애플리케이션 노트 | TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map | 2004. 5. 15 | |||
| 애플리케이션 노트 | AN-1056 STN Application Using FPD-Link | 2004. 5. 14 | |||
| 애플리케이션 노트 | AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines | 2004. 5. 14 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
FLINK3V8BT-85 — 시리얼라이저 및 디시리얼라이저 LVDS 장치의 FPD-Link 제품군용 평가 키트
The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.
The transmitter board accepts (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TSSOP (DGG) | 48 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.