DS90CR217
- 20 to 85 MHz Shift Clock Support
- 50% Duty Cycle on Receiver Output Clock
- Best-in-Class Set & Hold Times on TxINPUTs
- Low Power Consumption
- ±1V Common-Mode Range (Around +1.2V)
- Narrow Bus Reduces Cable Size and Cost
- Up to 1.785 Gbps Throughput
- Up to 223 Mbytes/sec Bandwidth
- 345 mV (typ) Swing LVDS Devices for Low EMI
- PLL Requires No External Components
- Rising Edge Data Strobe
- Compatible with TIA/EIA-644 LVDS Standard
- Low Profile 48-Lead TSSOP Package
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The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 21 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 1.785 Gbit/s (223 Mbytes/sec).
The narrow bus and LVDS signalling of the DS90CR217 is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | DS90CR217 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz datasheet (Rev. A) | 2013. 2. 19 | ||
| 애플리케이션 노트 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018. 11. 9 | |||
| 애플리케이션 노트 | Receiver Skew Margin for Channel Link I and FPD Link I Devices | PDF | HTML | 2016. 1. 13 | ||
| 애플리케이션 노트 | Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A) | 2013. 4. 26 | |||
| 설계 가이드 | Channel Link I Design Guide | 2007. 3. 29 | |||
| 애플리케이션 노트 | Multi-Drop Channel-Link Operation | 2004. 10. 4 | |||
| 애플리케이션 노트 | CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications | 1998. 10. 5 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TSSOP (DGG) | 48 | Ultra Librarian |
주문 및 품질
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