홈 로직 및 전압 변환 로직 게이트 전압 변환 게이트
홈
로직 및 전압 변환
로직 게이트
전압 변환 게이트

SN54SC4T08-SEP

활성

로직 레벨 시프터가 있는 방사능 내성, 4채널 2입력 양극 AND 게이트

지금 주문
데이터 시트

SN54SC4T08-SEP

활성
데이터 시트 지금 주문

제품 상세 정보

Technology family SCxT Number of channels 4 Vout (min) (V) 1.2 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type TTL-Compatible CMOS Output type Push-Pull Operating temperature range (°C) -55 to 125
Technology family SCxT Number of channels 4 Vout (min) (V) 1.2 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type TTL-Compatible CMOS Output type Push-Pull Operating temperature range (°C) -55 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Vendor item drawing available, VID V62/23620
  • Total ionizing dose characterized at 30 krad(Si)
    • Total ionizing dose characterized radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad(Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2 V to 5.5 V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2 V V CC
    • TTL compatible inputs:
      • Up translation:
        • 1.8-V – Inputs from 1.2 V
        • 2.5-V – Inputs from 1.8 V
        • 3.3-V – Inputs from 1.8 V, 2.5 V
        • 5.0-V – Inputs from 2.5 V, 3.3 V
      • Down translation:
        • 1.2-V – Inputs from 1.8 V, 2.5 V, 3.3 V, 5.0 V
        • 1.8-V – Inputs from 2.5 V, 3.3 V, 5.0 V
        • 2.5-V – Inputs from 3.3 V, 5.0 V
        • 3.3-V – Inputs from 5.0 V
  • 5.5 V tolerant input pins
  • Output drive up to 25 mA at 5-V
  • Latch-up performance exceeds 250 mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Extended product-change notification (PCN)
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification
  • Vendor item drawing available, VID V62/23620
  • Total ionizing dose characterized at 30 krad(Si)
    • Total ionizing dose characterized radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad(Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2 V to 5.5 V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2 V V CC
    • TTL compatible inputs:
      • Up translation:
        • 1.8-V – Inputs from 1.2 V
        • 2.5-V – Inputs from 1.8 V
        • 3.3-V – Inputs from 1.8 V, 2.5 V
        • 5.0-V – Inputs from 2.5 V, 3.3 V
      • Down translation:
        • 1.2-V – Inputs from 1.8 V, 2.5 V, 3.3 V, 5.0 V
        • 1.8-V – Inputs from 2.5 V, 3.3 V, 5.0 V
        • 2.5-V – Inputs from 3.3 V, 5.0 V
        • 3.3-V – Inputs from 5.0 V
  • 5.5 V tolerant input pins
  • Output drive up to 25 mA at 5-V
  • Latch-up performance exceeds 250 mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Extended product-change notification (PCN)
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification

The SN54SC4T08-SEP contains four independent 2- input AND Gates . Each gate performs the Boolean function Y = A × B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.2-V, 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). Additionally, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN54SC4T08-SEP contains four independent 2- input AND Gates . Each gate performs the Boolean function Y = A × B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.2-V, 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). Additionally, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
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기술 자료

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5개 모두 보기
유형 직함 날짜
* Data sheet SN54SC4T08-SEP Radiation-Tolerant, 1.2-V to 5.5-V, Quadruple 2-Input Positive-AND Gates With Integrated Translation datasheet (Rev. A) PDF | HTML 2023/08/11
* Radiation & reliability report SN54SC4T08-SEP Single Event Latch-Up Report PDF | HTML 2023/10/30
* Radiation & reliability report SN54SC4T08-SEP Production Flow and Reliability Report PDF | HTML 2023/08/23
* Radiation & reliability report SN54SC4T08-SEP Total Ionizing Dose Report PDF | HTML 2023/08/03
Application brief TI Space Enhanced Plastic Logic Overview and Applications in Low-Earth Orbit Satellite Platforms PDF | HTML 2024/09/10

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

사용 설명서: PDF | HTML
TI.com에서 구매 불가
시뮬레이션 모델

SN54SC4T08-SEP IBIS Model

SBAM502.ZIP (57 KB) - IBIS Model
다운로드
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
TSSOP (PW) 14 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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