인터페이스 RS-485 및 RS-422 트랜시버

SN65LBC176A-EP

활성

향상된 제품 차동 버스 트랜시버

제품 상세 정보

Number of receivers 1 Number of transmitters 1 Duplex Half Supply voltage (nom) (V) 5 Signaling rate (max) (MBits) 30 Fault protection (V) -10 to 15 Common-mode range (V) -7 to 12 Number of nodes 32 Isolated No Supply current (max) (µA) 15000 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Number of receivers 1 Number of transmitters 1 Duplex Half Supply voltage (nom) (V) 5 Signaling rate (max) (MBits) 30 Fault protection (V) -10 to 15 Common-mode range (V) -7 to 12 Number of nodes 32 Isolated No Supply current (max) (µA) 15000 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
SOIC (D) 8 29.4 mm² 4.9 x 6
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree
  • High-Speed Low-Power LinBiCMOS™ Circuitry Designed for Signaling Rates Up to 30 Mbps
  • Bus-Pin ESD Protection Exceeds 12-kV HBM
  • Compatible With ANSI Standard TIA/EIA-485-A and ISO 8482:1987(E)
  • Low Skew
  • Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments
  • Low Disabled Supply Current Requirements . . . 700 µA Maximum
  • Common Mode Voltage Range of –7 V to 12 V
  • Thermal-Shutdown Protection
  • Driver Positive and Negative Current Limiting
  • Open-Circuit Fail-Safe Receiver Design
  • Receiver Input Sensitivity ...±200 mV Max
  • Receiver Input Hysteresis . . . 50 mV Typ
  • Glitch-Free Power-Up and Power-Down Protection

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
Signaling rate by TIA/EIA-485-A definition restrict transition times to 30% of the bit length, and much higher signaling rates may be achieved without this requirement as displayed in the TYPICAL CHARACTERISTICS of this device.
LinBiCMOS and LinASIC are trademarks of Texas Instruments.

  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree
  • High-Speed Low-Power LinBiCMOS™ Circuitry Designed for Signaling Rates Up to 30 Mbps
  • Bus-Pin ESD Protection Exceeds 12-kV HBM
  • Compatible With ANSI Standard TIA/EIA-485-A and ISO 8482:1987(E)
  • Low Skew
  • Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments
  • Low Disabled Supply Current Requirements . . . 700 µA Maximum
  • Common Mode Voltage Range of –7 V to 12 V
  • Thermal-Shutdown Protection
  • Driver Positive and Negative Current Limiting
  • Open-Circuit Fail-Safe Receiver Design
  • Receiver Input Sensitivity ...±200 mV Max
  • Receiver Input Hysteresis . . . 50 mV Typ
  • Glitch-Free Power-Up and Power-Down Protection

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
Signaling rate by TIA/EIA-485-A definition restrict transition times to 30% of the bit length, and much higher signaling rates may be achieved without this requirement as displayed in the TYPICAL CHARACTERISTICS of this device.
LinBiCMOS and LinASIC are trademarks of Texas Instruments.

The SN65LBC176A-EP differential bus transceiver is a monolithic, integrated circuits designed for bidirectional data communication on multipoint bus-transmission lines. The SN65LBC176A-EP is designed for balanced transmission lines and is compatible with ANSI standard TIA/EIA-485-A and ISO 8482. The SN65LBC176A-EP offers improved switching performance over its predecessors without sacrificing significantly more power.

The SN65LBC176A-EP combines a 3-state, differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, which can externally connect together to function as a direction control. The driver differential outputs and the receiver differential inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. This port features wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications. Low device supply current can be achieved by disabling the driver and the receiver.

The SN65LBC176A-EP differential bus transceiver is a monolithic, integrated circuits designed for bidirectional data communication on multipoint bus-transmission lines. The SN65LBC176A-EP is designed for balanced transmission lines and is compatible with ANSI standard TIA/EIA-485-A and ISO 8482. The SN65LBC176A-EP offers improved switching performance over its predecessors without sacrificing significantly more power.

The SN65LBC176A-EP combines a 3-state, differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, which can externally connect together to function as a direction control. The driver differential outputs and the receiver differential inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. This port features wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications. Low device supply current can be achieved by disabling the driver and the receiver.

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관심 가지실만한 유사 제품

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SN65LBC176 활성 차동 버스 트랜시버 Catalog version

기술 자료

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3개 모두 보기
유형 직함 날짜
* Data sheet SN65LBC176A-EP: Differential Bus Transceivers datasheet (Rev. C) 2004/07/06
* VID SN65LBC176A-EP VID V6203671 2016/06/21
* Radiation & reliability report SN65LBC176AQDREP Reliability Report 2013/01/07

설계 및 개발

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시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
사용 설명서: PDF
패키지 CAD 기호, 풋프린트 및 3D 모델
SOIC (D) 8 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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