제품 상세 정보

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 18 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type Push-Pull Features Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Technology family ABT Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 18 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type Push-Pull Features Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Technology family ABT Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 56 190.647 mm² 18.42 x 10.35
  • Members of the Texas Instruments WidebusTM Family
  • B-Port Outputs Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA
    Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Package Options Include Plastic Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

    Widebus, EPIC-IIB, and UBT are trademarks of Texas Instruments Incorporated.

  • Members of the Texas Instruments WidebusTM Family
  • B-Port Outputs Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA
    Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Package Options Include Plastic Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

    Widebus, EPIC-IIB, and UBT are trademarks of Texas Instruments Incorporated.

These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB\ and CLKBA\) inputs.

For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB\ is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB\. Output-enable OEAB is active high. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses OEBA\, LEBA, and CLKBA\. The output enables are complementary (OEAB is active high and OEBA\ is active low).

The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

The SN54ABT162500 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT162500 is characterized for operation from -40°C to 85°C.

A-to-B data flow is shown: B-to-A flow is similar but uses OEBA\, LEBA, and CLKBA\.

Output level before the indicated steady-state input conditions were established

§ Output level before the indicated steady-state input conditions were established, provided that CLKAB\ was low before LEAB went low

These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB\ and CLKBA\) inputs.

For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB\ is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB\. Output-enable OEAB is active high. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses OEBA\, LEBA, and CLKBA\. The output enables are complementary (OEAB is active high and OEBA\ is active low).

The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

The SN54ABT162500 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT162500 is characterized for operation from -40°C to 85°C.

A-to-B data flow is shown: B-to-A flow is similar but uses OEBA\, LEBA, and CLKBA\.

Output level before the indicated steady-state input conditions were established

§ Output level before the indicated steady-state input conditions were established, provided that CLKAB\ was low before LEAB went low

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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
74ACT16861 활성 3상 출력을 지원하는 20비트 버스 트랜시버 Longer propagation delay (8ns), lower average drive strength (24mA)

기술 자료

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19개 모두 보기
유형 직함 날짜
* Data sheet 18-Bit Universal Bus Transceivers With 3-State Outputs datasheet (Rev. E) 1999/02/19
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
Application note Quad Flatpack No-Lead Logic Packages (Rev. D) 2004/02/16
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
Selection guide Advanced Bus Interface Logic Selection Guide 2001/01/09
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) 1997/06/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 1997/03/01
Application note Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 1996/12/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

패키지 CAD 기호, 풋프린트 및 3D 모델
SSOP (DL) 56 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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