SN74ABT18245A

Name: SN74ABT18245A
Brand: TI
SKU: SN74ABT18245A
Price: 4.675 USD

활성

18비트 버스 트랜시버를 지원하는 스캔 테스트 장치

지금 주문

데이터 시트

document-pdfAcrobat Scan Test Devices With 18-Bit Bus Transceivers datasheet (Rev. H) (영어)

SN74ABT18245A

활성

데이터 시트

지금 주문

제품 상세 정보

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

18

IOL (max) (mA)

64

IOH (max) (mA)

-32

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Partial power down (Ioff), Very high speed (tpd 5-10ns)

Technology family

ABT

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

18

IOL (max) (mA)

64

IOH (max) (mA)

-32

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Partial power down (Ioff), Very high speed (tpd 5-10ns)

Technology family

ABT

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DL)

56

190.647 mm² 18.42 x 10.35

TSSOP (DGG)

56

113.4 mm² 14 x 8.1

Members of the Texas Instruments SCOPE^TM Family of Testability Products
Members of the Texas Instruments Widebus^TM Family
Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
SCOPE^TM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions, CLAMP and HIGHZ
- Parallel-Signature Analysis at Inputs
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Device Identification
- Even-Parity Opcodes
State-of-the-Art EPIC-II B^TM BiCMOS Design Significantly Reduces Power Dissipation
Packaged in Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Packages

SCOPE, Widebus, and EPIC-IIB are trademarks of Texas Instruments Incorporated.

Members of the Texas Instruments SCOPE^TM Family of Testability Products
Members of the Texas Instruments Widebus^TM Family
Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
SCOPE^TM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions, CLAMP and HIGHZ
- Parallel-Signature Analysis at Inputs
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Device Identification
- Even-Parity Opcodes
State-of-the-Art EPIC-II B^TM BiCMOS Design Significantly Reduces Power Dissipation
Packaged in Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Packages

SCOPE, Widebus, and EPIC-IIB are trademarks of Texas Instruments Incorporated.

The 'ABT18245A scan test devices with 18-bit bus transceivers are members of the Texas Instruments SCOPE^TM testability integrated-
circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are 18-bit noninverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE^TM bus transceivers.

Data flow is controlled by the direction-control (DIR) and output-enable (OE\) inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE\ can be used to disable the device so that the buses are effectively isolated.

In the test mode, the normal operation of the SCOPE^TM bus transceivers is inhibited and the test circuitry is enabled to observe and control the input/output (I/O) boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins observe and control the operation of the test circuitry: test-data input (TDI), test-data output (TDO), test-mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT18245A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18245A is characterized for operation from -40°C to 85°C.

The 'ABT18245A scan test devices with 18-bit bus transceivers are members of the Texas Instruments SCOPE^TM testability integrated-
circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are 18-bit noninverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE^TM bus transceivers.

Data flow is controlled by the direction-control (DIR) and output-enable (OE\) inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE\ can be used to disable the device so that the buses are effectively isolated.

In the test mode, the normal operation of the SCOPE^TM bus transceivers is inhibited and the test circuitry is enabled to observe and control the input/output (I/O) boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins observe and control the operation of the test circuitry: test-data input (TDI), test-data output (TDO), test-mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT18245A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18245A is characterized for operation from -40°C to 85°C.

filter

기타 범용 트랜시버 찾기

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치와 유사한 기능

SN74ACT245

활성

TTL 호환 CMOS 입력 및 3상 출력을 지원하는 옥탈 버스 트랜시버 Longer propagation delay (8ns), lower average drive strength (24mA)

기술 자료

star

=TI에서 선정한 이 제품의 인기 문서

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21개 모두 보기

	유형	직함	날짜
*	Data sheet	Scan Test Devices With 18-Bit Bus Transceivers datasheet (Rev. H)	1999/02/19
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	2021/07/26
	Selection guide	Logic Guide (Rev. AB)	2017/06/12
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	2015/12/02
	User guide	LOGIC Pocket Data Book (Rev. B)	2007/01/16
	EVM User's guide	LASP Demo Board User's Guide	2005/11/01
	Application note	Programming CPLDs Via the 'LVT8986 LASP	2005/11/01
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	2004/07/08
	Application note	Selecting the Right Level Translation Solution (Rev. A)	2004/06/22
	Application note	Quad Flatpack No-Lead Logic Packages (Rev. D)	2004/02/16
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	2002/08/29
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	2002/05/10
	Selection guide	Advanced Bus Interface Logic Selection Guide	2001/01/09
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	1997/08/01
	Application note	Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)	1997/06/01
	Application note	Designing With Logic (Rev. C)	1997/06/01
	Application note	Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)	1997/03/01
	Application note	Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)	1996/12/01
	Application note	Input and Output Characteristics of Digital Integrated Circuits	1996/10/01
	Application note	Live Insertion	1996/10/01
	Application note	Understanding Advanced Bus-Interface Products Design Guide	1996/05/01