SN74GTL2014

Name: SN74GTL2014
Brand: TI
SKU: SN74GTL2014
Price: 0.332 USD

활성

GTL 트랜시버에 대한 4비트 LVTTL

지금 주문

데이터 시트

document-pdfAcrobat SN74GTL2014 4-Channel LVTTL to GTL Transceiver datasheet (Rev. A) (영어) PDF | HTML

SN74GTL2014

활성

데이터 시트

지금 주문

제품 상세 정보

Bits (#)

Data rate (max) (Mbps)

100

Topology

Open drain, Push-Pull

Direction control (typ)

Fixed-direction

Vin (min) (V)

Vin (max) (V)

3.6

Vout (min) (V)

0.8

Vout (max) (V)

3.6

Applications

GTL, SDIO

Features

Overvoltage tolerant inputs

Technology family

GTL

Supply current (max) (mA)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Bits (#)

Data rate (max) (Mbps)

100

Topology

Open drain, Push-Pull

Direction control (typ)

Fixed-direction

Vin (min) (V)

Vin (max) (V)

3.6

Vout (min) (V)

0.8

Vout (max) (V)

3.6

Applications

GTL, SDIO

Features

Overvoltage tolerant inputs

Technology family

GTL

Supply current (max) (mA)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

TSSOP (PW)

32 mm² 5 x 6.4

Operates as a GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+ Translator
The LVTTL Inputs are Tolerant up to 5.5 V Allowing Direct Access to TTL or 5 V CMOS
The GTL Input/Output Operate up to 3.6 V, Allowing the Device to be Used in High Voltage Open-Drain Applications
VREF Goes Down to 0.5 V for Low Voltage CPU Usage
Partial Power-Down Permitted
Latch-up Protection Exceed 500 mA per JESD78
Package Option: TSSOP14
–40°C to 85°C Operating Temperature Range
ESD Protection on All Terminals
- 2000 V HBM, JESD22-A114
- 1000 V CDM, IEC61000-4-2

Operates as a GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+ Translator
The LVTTL Inputs are Tolerant up to 5.5 V Allowing Direct Access to TTL or 5 V CMOS
The GTL Input/Output Operate up to 3.6 V, Allowing the Device to be Used in High Voltage Open-Drain Applications
VREF Goes Down to 0.5 V for Low Voltage CPU Usage
Partial Power-Down Permitted
Latch-up Protection Exceed 500 mA per JESD78
Package Option: TSSOP14
–40°C to 85°C Operating Temperature Range
ESD Protection on All Terminals
- 2000 V HBM, JESD22-A114
- 1000 V CDM, IEC61000-4-2

The SN74GTL2014 is a 4-channel translator to interface between 3.3-V LVTTL chip set I/O and Xeon processor GTL–/GTL/GTL+ I/O.

The SN74GTL2014 integrates ESD protection cells on all terminals and is available in a TSSOP package (5.0 mm × 4.4 mm). The device is characterized over the free air temperature range of –40°C to 85°C.

The SN74GTL2014 is a 4-channel translator to interface between 3.3-V LVTTL chip set I/O and Xeon processor GTL–/GTL/GTL+ I/O.

filter

기타 전압 변환기 찾기

다운로드 스크립트와 함께 비디오 보기 동영상

기술 자료

star

=TI에서 선정한 이 제품의 인기 문서

검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.

24개 모두 보기

	유형	직함		날짜
*	Data sheet	SN74GTL2014 4-Channel LVTTL to GTL Transceiver datasheet (Rev. A)	PDF \| HTML	2014/10/16
	Application note	Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators	PDF \| HTML	2024/07/12
	Application note	Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A)	PDF \| HTML	2024/07/03
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		2021/07/26
	Selection guide	Voltage Translation Buying Guide (Rev. A)		2021/04/15
	Selection guide	Logic Guide (Rev. AB)		2017/06/12
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015/12/02
	Application note	Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)		2015/04/30
	User guide	LOGIC Pocket Data Book (Rev. B)		2007/01/16
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004/07/08
	Application note	Selecting the Right Level Translation Solution (Rev. A)		2004/06/22
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		2002/08/29
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices		2002/05/10
	Application note	Logic in Live-Insertion Applications With a Focus on GTLP		2002/01/14
	User guide	GTLP/GTL Logic High-Performance Backplane Drivers Data Book (Rev. A)		2001/09/15
	Application note	Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)		2001/04/05
	Application note	Basic Design Considerations for Backplanes (Rev. B)		2001/04/05
	Selection guide	Advanced Bus Interface Logic Selection Guide		2001/01/09
	Application note	Fast GTLP Backplanes With the GTLPH1655 (Rev. A)		2000/09/19
	Application note	GTLP in BTL Applications		2000/07/31
	Application note	High-Performance Backplane Design With GTL+ (Rev. A)		1999/10/25
	Application note	GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A)		1997/03/01
	Application note	Understanding Advanced Bus-Interface Products Design Guide		1996/05/01
	Selection guide	Logic Guide (Rev. AC)	PDF \| HTML	1994/06/01