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TXG4042-Q1

미리 보기

차량용, ±40V, 4비트 고정 방향 접지 레벨 변환기, 2/2 구성

지금 주문
데이터 시트

TXG4042-Q1

미리 보기
데이터 시트 지금 주문

제품 상세 정보

Rating Catalog Technology family TXG Applications GPIO, I2S, PCM, SPI, UART Bits (#) 4 Configuration 2 Ch A to B 2 Ch B to A Data rate (max) (bps) 100000000 High input voltage (min) (V) 0.78 High input voltage (max) (V) 5.5 Vout (min) (V) 0 Vout (max) (V) 5.5 Output type 3-State Features AEC Q100, Partial power down (Ioff)
Rating Catalog Technology family TXG Applications GPIO, I2S, PCM, SPI, UART Bits (#) 4 Configuration 2 Ch A to B 2 Ch B to A Data rate (max) (bps) 100000000 High input voltage (min) (V) 0.78 High input voltage (max) (V) 5.5 Vout (min) (V) 0 Vout (max) (V) 5.5 Output type 3-State Features AEC Q100, Partial power down (Ioff)
X2QFN (RUC) 14 4 mm² 2 x 2
  • AEC-Q100 qualified for automotive applications
  • Will be available in wettable flank QFN (RUC) package
  • Supports DC ground shifts up to 40V
  • AC Noise Rejection of 80VPP up to 5MHz
  • CMTI of 1kV/µs
  • Low Prop Delay (<5ns) and Ch-Ch Skew (0.35ns)
  • Greater than 250Mbps
  • Low power consumption (0.65mA per channel at 1Mbps, 1.8V)
  • Fully configurable dual-rail design allows each port to operate from 1.71V to 5.5V
  • 4, 2, 1 channel devices with multiple configurations will be available
  • Two device variants:
    • TXG4041-Q1: 3 forward, 1 reverse
    • TXG4042-Q1: 2 forward, 2 reverse
  • Supports VCC disconnect feature (I/Os are forced into high-Z)
  • Schmitt-trigger inputs allows for slow and noisy signals
  • Inputs with integrated static pull-down resistors prevent channels from floating
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 4000V human-body model
    • 500V charged-device model
  • Package options provided:
    • RUC (X2QFN-14)
    • DYY (SOT-14)
    • DBQ (QSOP-16)
  • AEC-Q100 qualified for automotive applications
  • Will be available in wettable flank QFN (RUC) package
  • Supports DC ground shifts up to 40V
  • AC Noise Rejection of 80VPP up to 5MHz
  • CMTI of 1kV/µs
  • Low Prop Delay (<5ns) and Ch-Ch Skew (0.35ns)
  • Greater than 250Mbps
  • Low power consumption (0.65mA per channel at 1Mbps, 1.8V)
  • Fully configurable dual-rail design allows each port to operate from 1.71V to 5.5V
  • 4, 2, 1 channel devices with multiple configurations will be available
  • Two device variants:
    • TXG4041-Q1: 3 forward, 1 reverse
    • TXG4042-Q1: 2 forward, 2 reverse
  • Supports VCC disconnect feature (I/Os are forced into high-Z)
  • Schmitt-trigger inputs allows for slow and noisy signals
  • Inputs with integrated static pull-down resistors prevent channels from floating
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 4000V human-body model
    • 500V charged-device model
  • Package options provided:
    • RUC (X2QFN-14)
    • DYY (SOT-14)
    • DBQ (QSOP-16)

The TXG404x-Q1 is a 4-bit, fixed direction, non-galvanic based voltage and ground-level translator that can support both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ±40V. Compared to traditional level shifters, the TXG404x-Q1 family can solve the challenges of voltage translation across different ground levels. The Simplified Diagram shows a common use case where DC shift occurs between GNDA to GNDB due to parasitic resistance or capacitance.

VCCA is referenced to GNDA and VCCB is referenced to GNDB. Ax pins are referenced to VCCA logic level while Bx pins are referenced to VCCB logic levels. Both A port and B port can accept voltages from 1.71V to 5.5V. This device includes two enable pins that can place the respective outputs in a high-impedance state when the OE pin is connected to GND or left floating. In the event of input power or signal loss, the output is default low when OE is High (refer to ). The leakage between GNDA and GNDB is <30nA when VCC to GND is shorted.

The TXG404x-Q1 device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency and channel-to-channel skew. It can supress noise levels of 80VPP up to 5MHz (Figure 7-4). This device can support multiple interfaces such as SPI, UART, GPIO, and I2S.

The TXG404x-Q1 is a 4-bit, fixed direction, non-galvanic based voltage and ground-level translator that can support both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ±40V. Compared to traditional level shifters, the TXG404x-Q1 family can solve the challenges of voltage translation across different ground levels. The Simplified Diagram shows a common use case where DC shift occurs between GNDA to GNDB due to parasitic resistance or capacitance.

VCCA is referenced to GNDA and VCCB is referenced to GNDB. Ax pins are referenced to VCCA logic level while Bx pins are referenced to VCCB logic levels. Both A port and B port can accept voltages from 1.71V to 5.5V. This device includes two enable pins that can place the respective outputs in a high-impedance state when the OE pin is connected to GND or left floating. In the event of input power or signal loss, the output is default low when OE is High (refer to ). The leakage between GNDA and GNDB is <30nA when VCC to GND is shorted.

The TXG404x-Q1 device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency and channel-to-channel skew. It can supress noise levels of 80VPP up to 5MHz (Figure 7-4). This device can support multiple interfaces such as SPI, UART, GPIO, and I2S.
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기술 자료

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2개 모두 보기
유형 직함 날짜
* Data sheet TXG404x-Q1 4-bit , ± 40V Ground-Level Translator datasheet (Rev. A) PDF | HTML 2025/04/14
Product overview TI's Latest Ground-Level Translators PDF | HTML 2025/05/07

설계 및 개발

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평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
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  • 조립 위치

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