產品詳細資料

Sample rate (max) (Msps) 3000 Resolution (Bits) 7 Number of input channels 2 Interface type Parallel LVDS Analog input BW (MHz) 2000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.87 Power consumption (typ) (mW) 1900 Architecture Folding Interpolating SNR (dB) 43.2 ENOB (bit) 6.8 SFDR (dB) 61 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 3000 Resolution (Bits) 7 Number of input channels 2 Interface type Parallel LVDS Analog input BW (MHz) 2000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.87 Power consumption (typ) (mW) 1900 Architecture Folding Interpolating SNR (dB) 43.2 ENOB (bit) 6.8 SFDR (dB) 61 Operating temperature range (°C) -40 to 85 Input buffer No
HLQFP (NNB) 128 484 mm² 22 x 22
  • Single +1.9V ±0.1V Operation
  • Interleave Mode for 2x Sample Rate
  • Multiple ADC Synchronization Capability
  • Adjustment of Input Full-Scale Range, Clock Phase, and Offset
  • Choice of SDR or DDR Output Clocking
  • 1:1 or 1:2 Selectable Output Demux
  • Second DCLK Output
  • Duty Cycle Corrected Sample Clock
  • Test pattern
  • Single +1.9V ±0.1V Operation
  • Interleave Mode for 2x Sample Rate
  • Multiple ADC Synchronization Capability
  • Adjustment of Input Full-Scale Range, Clock Phase, and Offset
  • Choice of SDR or DDR Output Clocking
  • 1:1 or 1:2 Selectable Output Demux
  • Second DCLK Output
  • Duty Cycle Corrected Sample Clock
  • Test pattern

The ADC07D1520 is a dual, low power, high performance CMOS analog-to-digital converter. The ADC07D1520 digitizes signals to 7 bits of resolution at sample rates up to 1.5 GSPS. Its features include a test pattern output for system debug, a clock phase adjust, and selectable output demultiplexer modes. This device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 6.8 Effective Number of Bits (ENOB) with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10 -18 Code Error Rate (C.E.R.) Output formatting is offset binary and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demultiplexed Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demultiplexed Mode is selected, the output data rate on channels DI and DQ is at the same rate as the input sample clock. The two converters can be interleaved and used as a single 3 GSPS ADC.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a leaded or lead-free, 128-pin, thermally enhanced, exposed pad LQFP and operates over the Industrial (–40°C ≤ TA ≤ +85°C) temperature range.

The ADC07D1520 is a dual, low power, high performance CMOS analog-to-digital converter. The ADC07D1520 digitizes signals to 7 bits of resolution at sample rates up to 1.5 GSPS. Its features include a test pattern output for system debug, a clock phase adjust, and selectable output demultiplexer modes. This device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 6.8 Effective Number of Bits (ENOB) with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10 -18 Code Error Rate (C.E.R.) Output formatting is offset binary and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demultiplexed Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demultiplexed Mode is selected, the output data rate on channels DI and DQ is at the same rate as the input sample clock. The two converters can be interleaved and used as a single 3 GSPS ADC.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a leaded or lead-free, 128-pin, thermally enhanced, exposed pad LQFP and operates over the Industrial (–40°C ≤ TA ≤ +85°C) temperature range.

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類型 標題 日期
* Data sheet ADC07D1520 Low Pwr, 7-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Conv datasheet (Rev. A) 2012年 8月 20日
User guide ADC0XD1520RB Reference Board Users’ Guide 2012年 8月 22日

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模擬型號

ADC07D1520 IBIS Model

SLAM162.ZIP (19 KB) - IBIS Model
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ADC0xD1520RB Design Package

SNAR019.ZIP (15156 KB)
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HLQFP (NNB) 128 Ultra Librarian

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