ADC08B3000
- Single +1.9V ±0.1V Operation
- Choice of SDR or DDR Output Clocking
- Internal selectable 4K Data Buffer
- Serial Interface for Extended Control
- Adjustment of Input Full-Scale Range, Offset and Clock Phase
- Duty Cycle Corrected Sample Clock
- Test Pattern Output Capability
Key Specifications
- Resolution: 8 Bits
- Max Conversion Rate: 3 Gsps (min)
- Code Error Rate: 10-18 (typ)
- ENOB @ 748 MHz Input: 7.1 Bits (typ)
- SNR @ 748 MHz: 44.9 dB (typ)
- Full Power Bandwidth: 3 GHz (typ)
- Power Consumption
- Full Power Capure: 1.6 W (typ)
- Power Down Mode: 25 mW (typ)
All trademarks are the property of their respective owners.
The ADC08B3000 is a single, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sample rates up to 3.4 Gigasamples Per Second, (Gsps). Consuming a typical 1.6 Watts at 3 Gsps from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the calibration scheme enable an excellent response of all dynamic parameters up to Nyquist, producing a high 7.1 Effective Number Of Bits, (ENOB), with a 748 MHz input signal and a 3 GHz sample rate while providing a 10-18 Code Error Rate. A sample rate of 3 Gsps is achieved by interleaving two ADCs, each operating at 1.5 Gsps. Output formatting is offset binary. The device contains a 4K Capture Buffer with output on two 8-bit Low Voltage CMOS (LVCMOS) output buses at rates up to 200MHz.
The converter typically consumes less than 25 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | ADC08B3000 8-Bit, 3 GSPS, High Perf Low Pwr ADC w/4K Buffer datasheet (Rev. M) | 2013年 4月 18日 | |
User guide | Single low power, ultra high speed CMOS A D Converter with data buffer | 2012年 1月 25日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
WAVEVISION4 — 資料採集和分析軟體
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
HLQFP (NNB) | 128 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點