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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC12DC105

現行

雙通道、12 位元、105-MSPS、1.0-GHz 輸入頻寬類比轉數位轉換器 (ADC)

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產品規格表

ADC12DC105

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 105 Resolution (Bits) 12 Number of input channels 2 Interface type Parallel CMOS Analog input BW (MHz) 1000 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 800 Architecture Pipeline SNR (dB) 71 ENOB (Bits) 11.5 SFDR (dB) 90 Operating temperature range (°C) -45 to 85 Input buffer No
Sample rate (max) (Msps) 105 Resolution (Bits) 12 Number of input channels 2 Interface type Parallel CMOS Analog input BW (MHz) 1000 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 800 Architecture Pipeline SNR (dB) 71 ENOB (Bits) 11.5 SFDR (dB) 90 Operating temperature range (°C) -45 to 85 Input buffer No
WQFN (NKA) 60 81 mm² 9 x 9
  • Internal Sample-and-Hold Circuit and Precision Reference
  • Low Power Consumption
  • Clock Duty Cycle Stabilizer
  • Single +3.0V or +3.3V Supply Operation
  • Power-Down Mode
  • Offset Binary or 2's Complement Output Data Format
  • 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)

Key Specifications

  • High IF Sampling Receivers
  • Wireless Base Station Receivers
  • Test and Measurement Equipment
  • Communications Instrumentation
  • Portable Instrumentation

All trademarks are the property of their respective owners.

  • Internal Sample-and-Hold Circuit and Precision Reference
  • Low Power Consumption
  • Clock Duty Cycle Stabilizer
  • Single +3.0V or +3.3V Supply Operation
  • Power-Down Mode
  • Offset Binary or 2's Complement Output Data Format
  • 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)

Key Specifications

  • High IF Sampling Receivers
  • Wireless Base Station Receivers
  • Test and Measurement Equipment
  • Communications Instrumentation
  • Portable Instrumentation

All trademarks are the property of their respective owners.

The ADC12DC105 is a high-performance CMOS analog-to-digital converter capable of converting two analog input signals into 12-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC12DC080/105 may be operated from a single +3.0V or +3.3V power supply. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs provide a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC12DC105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles.

The ADC12DC105 is available in a 60-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.

The ADC12DC105 is a high-performance CMOS analog-to-digital converter capable of converting two analog input signals into 12-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC12DC080/105 may be operated from a single +3.0V or +3.3V power supply. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs provide a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC12DC105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles.

The ADC12DC105 is available in a 60-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.
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類型 標題 日期
* Data sheet ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs datasheet (Rev. B) 2013年 3月 15日
User guide ADC14DC105EB and ADC12DC105EB Evaluation Board User Guide (Rev. A) 2013年 10月 11日

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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WQFN (NKA) 60 Ultra Librarian
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