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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC12SJ800

現行

具有 JESD204C 介面的單通道、12 位元、800-MSPS 類比轉數位轉換器 (ADC)

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產品規格表

ADC12SJ800

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 800 Resolution (Bits) 12 Number of input channels 1 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 830 Architecture Folding Interpolating SNR (dB) 57.6 ENOB (Bits) 9 SFDR (dB) 62 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 800 Resolution (Bits) 12 Number of input channels 1 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 830 Architecture Folding Interpolating SNR (dB) 57.6 ENOB (Bits) 9 SFDR (dB) 62 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 800MSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (97 MHz): 57.6dBFS
    • ENOB (97 MHz): 9 Bits
    • SFDR (97 MHz): 62dBFS
    • Noise floor (–20dBFS): –146.1dBFS/Hz
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (800MSPS):
    • Quad Channel: 415mW / channel
    • Dual channel: 555mW / channel
    • Single channel: 830mW
  • Power supplies: 1.1V, 1.9V
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 800MSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (97 MHz): 57.6dBFS
    • ENOB (97 MHz): 9 Bits
    • SFDR (97 MHz): 62dBFS
    • Noise floor (–20dBFS): –146.1dBFS/Hz
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (800MSPS):
    • Quad Channel: 415mW / channel
    • Dual channel: 555mW / channel
    • Single channel: 830mW
  • Power supplies: 1.1V, 1.9V

ADC12xJ800 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800 ideally suited for a variety of multi-channel communications and test systems.

Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

ADC12xJ800 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800 ideally suited for a variety of multi-channel communications and test systems.

Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
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類型 標題 日期
* Data sheet ADC12xJ800 Quad, Dual, Single Channel, 800MSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. A) PDF | HTML 2024年 10月 18日
Application note Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends PDF | HTML 2025年 3月 28日
Application note Evaluating High-Speed, RF ADC Converter Front-end Architectures PDF | HTML 2025年 3月 26日

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ADC12QJ1600EVM — 具有 JESD204C 介面且適用於四通道、12 位元、1.6GSPS ADC 的 ADC12QJ1600 評估模組

ADC12QJ1600 評估模組 (EVM) 專為評估 ADC12QJ1600-Q1 系列高速類比轉數位轉換器 (ADC) 所設計。本 EVM 搭載 ADC12QJ1600-Q1 晶片，該晶片為具備 JESD204B 介面的 12 位元、四通道 1.6GSPS ADC，可評估 12 位元系列中所有取樣率之單通道、雙通道及四通道車用或工業級裝置。
使用指南: PDF
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開發板

TSW12QJ1600EVM — ADC12QJ1600-Q1 8 通道（兩個同步 4 通道）12 位元 1.6GSPS JESD204C 介面 ADC 評估模組

TSW12QJ1600 評估模組 (EVM) 專為評估 ADC12QJ1600-Q1 系列高速類比轉數位轉換器 (ADC) 所設計，並提供多種前端配置選項。本 EVM 搭載雙通道 ADC12QJ1600-Q1 晶片，該晶片為具備 JESD204B 介面的 12 位元、四通道 1.6GSPS ADC，可進行以下評估項目：多重 ADC 同步運作、確定性延遲測試、搭配不同前端選項（交流耦合變壓器配置；搭配 LMH32401 的直流耦合選項）的 ADC 性能測試。此設計也示範如何透過菊鏈將 PLL 參考輸出（PLLREFO+、PLLREFO-）從一個 ADC 鏈結至另一個 (...)
使用指南: PDF
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ADC12QJ1600 IBIS-AMI Model

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