產品詳細資料

Sample rate (max) (Msps) 170 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 1100 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 781 Architecture Pipeline SNR (dB) 67.9 ENOB (bit) 11 SFDR (dB) 85.8 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 170 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 1100 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 781 Architecture Pipeline SNR (dB) 67.9 ENOB (bit) 11 SFDR (dB) 85.8 Operating temperature range (°C) -40 to 85 Input buffer No
WQFN (RHS) 48 49 mm² 7 x 7
  • 1.1 GHz Full Power Bandwidth
  • Internal Sample-and-Hold Circuit
  • Internal Precision 1.0V Reference
  • Single-Ended or Differential Clock Modes
  • Clock Duty Cycle Stabilizer
  • Dual +3.3V and +1.8V Supply Operation
  • Power-Down and Sleep Modes
  • Offset Binary or 2's Complement Output Data Format
  • LVDS Outputs
  • Pin-Compatible: ADC14V155
  • 48-Pin WQFN Package, (7x7x0.8mm, 0.5mm Pin-Pitch)

Key Specifications

  • Resolution: 12 Bits
  • Conversion Rate: 170 MSPS
  • SNR (fIN = 70 MHz): 67.2 dBFS (Typ)
  • SFDR (fIN = 70 MHz): 85.8 dBFS (Typ)
  • ENOB (fIN = 70 MHz): 10.9 Bits (Typ)
  • Full Power Bandwidth: 1.1 GHZ (Typ)
  • Power Consumption: 781 mW (Typ)

All trademarks are the property of their respective owners.

  • 1.1 GHz Full Power Bandwidth
  • Internal Sample-and-Hold Circuit
  • Internal Precision 1.0V Reference
  • Single-Ended or Differential Clock Modes
  • Clock Duty Cycle Stabilizer
  • Dual +3.3V and +1.8V Supply Operation
  • Power-Down and Sleep Modes
  • Offset Binary or 2's Complement Output Data Format
  • LVDS Outputs
  • Pin-Compatible: ADC14V155
  • 48-Pin WQFN Package, (7x7x0.8mm, 0.5mm Pin-Pitch)

Key Specifications

  • Resolution: 12 Bits
  • Conversion Rate: 170 MSPS
  • SNR (fIN = 70 MHz): 67.2 dBFS (Typ)
  • SFDR (fIN = 70 MHz): 85.8 dBFS (Typ)
  • ENOB (fIN = 70 MHz): 10.9 Bits (Typ)
  • Full Power Bandwidth: 1.1 GHZ (Typ)
  • Power Consumption: 781 mW (Typ)

All trademarks are the property of their respective owners.

The ADC12V170 is a high-performance CMOS analog-to-digital converter with LVDS outputs. It is capable of converting analog input signals into 12-Bit digital words at rates up to 170 Mega Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual Data Rate) format; this allows both edges of the output clock to be utilized while achieving a smaller package size. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC12V170 operates from dual +3.3V and +1.8V power supplies and consumes 781 mW of power at 170 MSPS.

The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 15 mW while still allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes 50 mW of power and has a faster wake-up time.

The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC12V170 can be operated with an external reference.

Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of input clock duty cycles.

The ADC12V170 is pin-compatible with the ADC14V155. It is available in a 48-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.

The ADC12V170 is a high-performance CMOS analog-to-digital converter with LVDS outputs. It is capable of converting analog input signals into 12-Bit digital words at rates up to 170 Mega Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual Data Rate) format; this allows both edges of the output clock to be utilized while achieving a smaller package size. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC12V170 operates from dual +3.3V and +1.8V power supplies and consumes 781 mW of power at 170 MSPS.

The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 15 mW while still allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes 50 mW of power and has a faster wake-up time.

The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC12V170 can be operated with an external reference.

Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of input clock duty cycles.

The ADC12V170 is pin-compatible with the ADC14V155. It is available in a 48-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.

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* Data sheet ADC12V170 12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs datasheet (Rev. F) 2013年 4月 19日
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 2024年 4月 30日
User guide ADC12V170: 12-Bit, 170 MSPS ADC with LVDS Outputs User Guide 2012年 2月 21日

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