ADC3244E

現行

具有延伸溫度範圍的雙通道 14 位元 125 MSPS 類比轉數位轉換器 (ADC)

立即訂購

產品規格表

document-pdfAcrobat ADC3244E Dual-channel, 14-bit, 125-MSPS analog-to-digital converter datasheet (英文) PDF | HTML

ADC3244E

現行

產品規格表

立即訂購

產品詳細資料

Sample rate (max) (Msps)

125

Resolution (Bits)

14

Number of input channels

2

Interface type

Serial LVDS

Analog input BW (MHz)

540

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

232

Architecture

Pipeline

SNR (dB)

73.3

ENOB (Bits)

11.8

SFDR (dB)

94

Operating temperature range (°C)

-50 to 105

Input buffer

No

Sample rate (max) (Msps)

125

Resolution (Bits)

14

Number of input channels

2

Interface type

Serial LVDS

Analog input BW (MHz)

540

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

232

Architecture

Pipeline

SNR (dB)

73.3

ENOB (Bits)

11.8

SFDR (dB)

94

Operating temperature range (°C)

-50 to 105

Input buffer

No

VQFN (RGZ)

48

49 mm² (7 mm × 7 mm)

Dual channel
14-bit resolution
Single supply: 1.8 V
Serial LVDS interface (SLVDS)
Flexible input clock buffer with divide-by-1, -2, -4
SNR = 72.4 dBFS, SFDR = 87 dBc at
f_IN = 70 MHz
Ultra-low power consumption:
- 116 mW/Ch at 125 MSPS
Channel isolation: 105 dB
Internal dither and chopper
Support for multichip synchronization
Pin-to-pin compatible with 12-bit version
Package: VQFN-48 (7 mm × 7 mm)
Extended temperature range: –50°C to +105°C

Dual channel
14-bit resolution
Single supply: 1.8 V
Serial LVDS interface (SLVDS)
Flexible input clock buffer with divide-by-1, -2, -4
SNR = 72.4 dBFS, SFDR = 87 dBc at
f_IN = 70 MHz
Ultra-low power consumption:
- 116 mW/Ch at 125 MSPS
Channel isolation: 105 dB
Internal dither and chopper
Support for multichip synchronization
Pin-to-pin compatible with 12-bit version
Package: VQFN-48 (7 mm × 7 mm)
Extended temperature range: –50°C to +105°C

The ADC3244E is a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS analog-to-digital converter (ADC). The device is designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design, and the SYSREF input enables complete system synchronization.

The ADC3244E supports serial, low-voltage, differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where the data from each ADC are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

The ADC3244E is a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS analog-to-digital converter (ADC). The device is designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design, and the SYSREF input enables complete system synchronization.

The ADC3244E supports serial, low-voltage, differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where the data from each ADC are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

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