AFE7906
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- Six RF sampling 14 bit, 3GSPS ADCs
- Maximum RF signal bandwidth:
- 4 ADCs: 1200MHz per ADC
- 6 ADCs: 600MHz per ADC
- RF frequency range: 5MHz - 12GHz
- Digital step attenuators (DSA): 25dB range, 0.5dB steps
- Single DDC (on 6 channels) or dual-band DDCs (on 4 channels)
- 16x NCOs per DDC channel
- Optional Internal PLL/VCO for ADC clocks or external clock at ADC sample rate
- Sysref alignment detector
- SerDes data interface:
- JESD204B and JESD204C compatible
- 8 SerDes transmitters up to 29.5Gbps
- Subclass 1 multi-device synchronization
- Package: 17mm × 17mm FCBGA, 0.8mm pitch
The AFE7906 is a high performance, wide bandwidth multi-channel receiver, integrating six RF Sampling ADCs. With operation up to 12GHz, this device enables direct RF sampling in the L, S, C and X-band frequency ranges without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multi-mission systems.
Each receiver chain includes a 25dB range DSA (Digital Step Attenuator), followed by a 3GSPS ADC (analog-to-digital converter). Four receiver channels have an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200MHz for four RX or 600MHz.
The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the device clock.
Each receiver chain includes a 25dB range DSA (Digital Step Attenuator), followed by a 3GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200MHz for four RX without FB paths or 600MHz with two FB paths (1200MHz BW each).
The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the device clock.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | AFE7906 6-Channel, 5MHz to 12GHz RF Sampling Receiver with 3GSPS ADCs datasheet (Rev. D) | PDF | HTML | 2025/5/2 | ||
| 應用說明 | AFE79xx Linux Driver | PDF | HTML | 2026/7/30 | |||
| 應用說明 | AFE79xx Bringup Using HDL Module Without Microcontroller | PDF | HTML | 2025/8/14 | |||
| 應用說明 | Debugging AFE7950 for Run Time and Post Bring-Up Failure | PDF | HTML | 2024/6/28 | |||
| 使用指南 | AFE79xx SPI Bringup Guide With Xilinx FPGAs (Rev. A) | PDF | HTML | 2024/5/5 | |||
| 應用說明 | Determining Optimal Receive Buffer Delay in JESD204B and JESD204C Receivers | PDF | HTML | 2022/7/7 | |||
| 應用說明 | AFE7950 Super-Heterodyne Solution for K-Band | PDF | HTML | 2022/2/15 | |||
| 應用說明 | How to Achieve Frequency Hopping with the AFE79xx | 2020/7/2 |
設計與開發
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AFE7900EVM — 適用於四傳輸、六接收、5-MHz 至 7400-MHz、射頻取樣 AFE 的 AFE7900 評估模組
AFE7900 系列評估模組 (EVM) 是靈活的射頻取樣收發器平台,可配置為支援最多同時四個發射、四個接收與兩個回饋 (4T4R+2FB) 通道。此 EVM 設計可介接以下所示 TI 模式/擷取卡解決方案 (分開販售) 以及許多符合 FPGA FMC 標準的開發套件。
AFE79XX-HSC-DESIGN — AFE79xx family high-speed transceiver design & support files
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCBGA (ALK) | 400 | Ultra Librarian |
| FCBGA (ABJ) | 400 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。