CDCP1803
- Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs
- Programmable Output Divider for Two LVPECL Outputs
- Low-Output Skew 15 ps (Typical)
- VCC Range 3 V–3.6 V
- Signaling Rate Up to 800-MHz LVPECL
- Differential Input Stage for Wide Common-Mode Range
- Provides VBB Bias Voltage Output for Single-Ended Input Signals
- Receiver Input Threshold ±75 mV
- 24-Terminal QFN Package (4 mm × 4 mm)
- Accepts Any Differential Signaling:
LVDS, HSTL, CML, VML, SSTL-2, and
Single-Ended: LVTTL/LVCMOS
The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0] with minimum skew for clock distribution. The CDCP1803 is specifically designed for driving 50-Ω transmission lines.
The CDCP1803 has three control terminals, S0, S1, and S2, to select different output mode settings; see for details. The CDCP1803 is characterized for operation from –40°C to 85°C. For use in single-ended driver applications, the CDCP1803 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference.
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檢視所有 2 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | 1:3 LVPECL Clock Buffer with Programmable Divider, CDCP1803 datasheet (Rev. F) | 2013年 12月 4日 | |
| Application note | Dual Purposes: Data Buffer, The Other Face of CDCP1803 | 2004年 8月 13日 |
設計與開發
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模擬工具
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| 封裝 | 引腳 | 下載 |
|---|---|---|
| VQFN (RGE) | 24 | 檢視選項 |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。