開發模組 (EVM) 的 GUI
CDCUN1208LP
- Supports PCIe Gen1, Gen2, Gen3
- Configuration Options (Through Pins or SPI/I2C):
- Input Type (HCSL, LVDS, LVCMOS)
- Output Type (HCSL, LVDS, LVCMOS)
- Signal Edge Rate (Slow, Medium, Fast)
- Clock Input Divide Value (/1, /2, /4, /8) – IN2 Only
- Low-Power Consumption and Power Management Features, Including 1.8-V Operation and Output Enable Control
- Integrated Voltage Regulators to Improve PSNR
- Excellent Additive Jitter Performance
- 200 fs RMS (10 kHz to 20 MHz), LVDS at
100 MHz - 160 fs RMS (10 kHz to 20 MHz), HCSL at
100 MHz
- 200 fs RMS (10 kHz to 20 MHz), LVDS at
- Maximum Operating Frequency:
- Differential Mode: up to 400 MHz
- LVCMOS Mode: up to 250 MHz
- ESD Protection Exceeds 2-kV HBM, 500-V CDM
- Industrial Temperature Range (–40°C to 85°C)
- Wide Supply Range (1.8 V, 2.5 V, or 3.3 V)
The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/single-ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with edge-rate control. The clock buffer supports PCIe Gen1, Gen2 and Gen3. One of the device inputs includes a divider that provides divide values of /1, /2, /4, or /8. The CDCUN1208LP is offered in a 32-pin QFN package, reducing the solution footprint. The device is flexible and easy to use. The state of certain pins determines device configuration at power up. Alternately, the CDCUN1208LP provides a SPI/I2C port with which a host processor controls device settings. The CDCUN1208LP delivers excellent additive jitter performance, and low power consumption. The output section includes four dedicated supply pins enabling the operation of output ports from different power supply domains. This provides the ability to clock devices switching at different LVCMOS levels without the need for external logic level translation circuitry.
技術文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 2 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDCUN1208LP 400-MHz Low Power 2:8 Fan-Out Buffer With Universal Inputs and Outputs datasheet (Rev. D) | PDF | HTML | 2019年 4月 18日 |
| EVM User's guide | CDCUN1208LP EVM User's Guide | 2012年 4月 4日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
CDCUN1208LPEVM — CDCUN1208LP 評估模組
The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/ single ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with clock edge rate control. One of the device inputs includes a divider that provides divide values of /1, /2, /4, and (...)
使用指南: PDF
設計工具
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RHB) | 32 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。