CSD25501F3

現行

-20V、P 通道 NexFET™ 功率 MOSFET、單 LGA 0.6mm x 0.7mm、76mOhm、閘極 ESD 防護

產品詳細資料

VDS (V) -20 VGS (V) -20 Type P-channel Configuration Single Rds(on) at VGS=4.5 V (max) (mΩ) 76 Rds(on) at VGS=2.5 V (max) (mΩ) 125 VGSTH typ (typ) (V) -0.75 QG (typ) (nC) 1.02 QGD (typ) (nC) 0.09 QGS (typ) (nC) 0.45 ID - silicon limited at TC=25°C (A) 3.6 Logic level Yes Rating Catalog Operating temperature range (°C) -55 to 150
VDS (V) -20 VGS (V) -20 Type P-channel Configuration Single Rds(on) at VGS=4.5 V (max) (mΩ) 76 Rds(on) at VGS=2.5 V (max) (mΩ) 125 VGSTH typ (typ) (V) -0.75 QG (typ) (nC) 1.02 QGD (typ) (nC) 0.09 QGS (typ) (nC) 0.45 ID - silicon limited at TC=25°C (A) 3.6 Logic level Yes Rating Catalog Operating temperature range (°C) -55 to 150
PICOSTAR (YJN) 3 0.414 mm² (0.69 mm × 0.6 mm)
  • Low on-resistance
  • Ultra-low Qg and Qgd
  • Ultra-small footprint
    • 0.7mm × 0.6mm
  • Low profile
    • 0.22mm max height
  • Integrated ESD protection diode
  • Lead and halogen free
  • RoHS compliant
  • Low on-resistance
  • Ultra-low Qg and Qgd
  • Ultra-small footprint
    • 0.7mm × 0.6mm
  • Low profile
    • 0.22mm max height
  • Integrated ESD protection diode
  • Lead and halogen free
  • RoHS compliant

This –20V, 64mΩ, P-Channel FemtoFET™ MOSFET is designed and optimized to minimize the footprint in many handheld and mobile applications. This technology is capable of replacing standard small signal MOSFETs while providing a substantial reduction in footprint size. The integrated 10kΩ clamp resistor (RC) allows the gate voltage (VGS) to be operated above the maximum internal gate oxide value of –6V, depending on duty cycle. The gate leakage (IGSS) through the diode increases as VGS is increased above –6V.

This –20V, 64mΩ, P-Channel FemtoFET™ MOSFET is designed and optimized to minimize the footprint in many handheld and mobile applications. This technology is capable of replacing standard small signal MOSFETs while providing a substantial reduction in footprint size. The integrated 10kΩ clamp resistor (RC) allows the gate voltage (VGS) to be operated above the maximum internal gate oxide value of –6V, depending on duty cycle. The gate leakage (IGSS) through the diode increases as VGS is increased above –6V.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 CSD25501F3 –20V P-Channel FemtoFET™ MOSFET datasheet (Rev. C) PDF | HTML 2024/6/24
Application brief Estimating Leakage Currents of Power MOSFETs PDF | HTML 2025/10/31
應用說明 MOSFET Support and Training Tools (Rev. G) PDF | HTML 2025/10/27
應用說明 Semiconductor and IC Package Thermal Metrics (Rev. D) PDF | HTML 2024/3/25
應用說明 Using MOSFET Transient Thermal Impedance Curves In Your Design PDF | HTML 2023/12/18
應用說明 Solving Assembly Issues with Chip Scale Power MOSFETs PDF | HTML 2023/12/14
應用說明 Using MOSFET Safe Operating Area Curves in Your Design PDF | HTML 2023/3/13
Application brief Tips for Successfully Paralleling Power MOSFETs PDF | HTML 2022/5/31
設計指南 FemtoFET Surface Mount Guide (Rev. D) 2016/7/7

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

支援軟體

LOAD-SWITCH-FET-LOSS-CALC — Power Loss Calculation Tool for Load Switch

快速取捨尺寸、成本和性能,以根據應用條件選擇最佳 MOSFET。
支援產品和硬體
模擬型號

CSD25501F3 Unencrypted PSpice Model (Rev. A)

SLPM337A.ZIP (4 KB) - PSpice 模型
支援產品和硬體
參考設計

TIDA-010070 — 適用於低電壓伺服驅動的受保護 DC 匯流排輸入電源和控制電源供應參考設計

此參考設計採用 ORing 控制器 LM5050-1,提供反極性與反向電流保護。搭配 LM5069 熱插拔控制器,可實現過電流、過電壓、欠電壓保護及突波電流限制。此設計亦提供控制電子元件的電源軌,包括閘極驅動器、編碼器及 MCU 電路。
支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
PICOSTAR (YJN) 3 Ultra Librarian

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